參數(shù)資料
型號: IDT82V3280PFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 114/171頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝: 1
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 14:9
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
其它名稱: 82V3280PFG
IDT82V3280
WAN PLL
Typical Application
47
December 9, 2008
4
TYPICAL APPLICATION
The device supports Master / Slave application, as shown in
Figure 15. Typical Application
4.1
MASTER / SLAVE APPLICATION
Master / Slave application is only supported by the T0 path of the
device.
In Master / Slave application, two devices should be used together.
Of the two devices, one is configured as the Master and the other is con-
figured as the Slave. Refer to Chapter 3.14 Master / Slave Configuration
for details.
BITS/SSU
Timing Module
Stratum 2/3E
IDT82V3288
BITS/SSU
Timing Module
Stratum 2/3E
IDT82V3288
PRS
(Primary Reference Source)
Stratum
2/3E/3/SMC/SEC
Module
IDT82V3280
Stratum
2/3E/3/SMC/SEC
Module
IDT82V3280
Line Timing
Master/Slave
Typical 19.44 MHz
and other OC-N clock
155.52 Mbit/s
Line Card
IDT82V3255
622.08 Mbit/s
Line Card
IDT82V3255
2.5 Gbit/s
Line Card
IDT82V3255
10 Gbit/s
Line Card
IDT82V3255
Central Clock
Modules
Typical 8 kHz/1.544 MHz/2.048 MHz
SDH/SONET
or other Equipment
Timing System
Typical 19.44 MHz
and other OC-N clock
Typical 19.44
MHz and other
OC-N clock
Typical 19.44
MHz and other
OC-N clock
. . .
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