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參數(shù)資料
| 型號(hào)： | IDT82V3001APVG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 6/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN W/SGL REF INP 56-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類(lèi)型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | WAN |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 32.768MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | 82V3001APVG8 |
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FUNCTIONAL DESCRIPTION
14
October 15, 2008
IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
3.5
DPLL BLOCK
As shown in Figure - 8, the DPLL Block consists of a Phase Detector,
a Limiter, a Loop Filter, a Digital Control Oscillator and Dividers.
Figure - 8 DPLL Block Diagram
3.5.1
PHASE DETECTOR (PHD)
In Normal Mode, the Phase Detector compares the virtual reference
signal from the TIE Control Circuit with the feedback signal from the
Frequency Select Circuit, and outputs an error signal corresponding to
the phase difference between the two. This error signal is then sent to
the Limiter circuit for phase slope control.
The feedback signal can be 8 kHz, 2.048 MHz or 1.544 MHz, as
selected by F_sel1 and F_sel0 pins. Refer to Table - 3 for details.
In Freerun or Holdover Mode, the Frequency Select Circuit, the
Phase Detector and the Limiter are not active and the input reference
signal is not used.
3.5.2
LIMITER
The Limiter is used to ensure that the DPLL responds to all input
transient conditions with a maximum output phase slope of 5 ns per 125
s. This well meets AT&T TR62411 and Telcordia GR-1244-CORE
specifications, which specify the maximum phase slope of 7.6 ns per
125 s and 81 ns per 1.326 ms respectively.
In Normal Mode, the Limiter receives the error signal from the Phase
Detector, limits the phase slope within 5 ns per 125 s and sends the
limited signal to the Loop Filter.
The fast lock mode is a submode of Normal Mode. By setting the
FLOCK pin to high, the device will enter fast lock mode. In this mode,
the Limiter is disabled and the DPLL will lock to the incoming reference
within 500 ms.
3.5.3
LOOP FILTER
The Loop Filter ensures that the jitter transfer meets ETS 300 011
and AT&T TR62411 requirements. This Loop Filter works similarly to a
first order low pass filter with 2.1 Hz cutoff frequency for the three valid
input reference signals (8 kHz, 2.048 MHz or 1.544 MHz).
The output of the Loop Filter goes to the Digital Control Oscillator
directly or via the Fraction blocks, in which E1, T1 and C6 signals are
generated.
Di
gital
Contr
ol
Oscillator
C32o
C16o
C8o
C4o
C2o
C3o
C6o
F0o
F8o
RSP
TSP
F16o
C1.5o
F32o
Output Interface
T1_Divider
E1_Divider
C6_Divider
Frequency
Selection
Circuit
Phase
Detector
Virtual Reference
Loop Filter
Fraction_C6
Fraction_T1
24.704 MHz
32.768 MHz
25.248 MHz
Feedback
Signal
Limiter
FLOCK
F_sel1 F_sel0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3002A | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A_08 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A-01PVG | 功能描述:IC PLL WAN T1/E1 56SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT |
| IDT82V3002A-01PVG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN T1/E1 56SSOP |
| IDT82V3002APV | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
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