參數(shù)資料
型號(hào)： IDT82V3001APVG8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 27/28頁(yè)
文件大小： 0K
描述： IC PLL WAN W/SGL REF INP 56-SSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
主要目的： WAN
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:14
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 32.768MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 56-SSOP
包裝： 帶卷 (TR)
其它名稱： 82V3001APVG8
PIN DESCRIPTION
8
October 15, 2008
IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
C32o
(CMOS) O
25
Clock 32.768 MHz.
This output is a 32.768 MHz clock used for ST-BUS operation.
C16o
(CMOS) O
24
Clock 16.384 MHz.
This output is a 16.384 MHz clock used for ST-BUS operation.
C8o
(CMOS) O
23
Clock 8.192 MHz.
This output is an 8.192 MHz clock used for ST-BUS operation.
C4o
(CMOS) O
20
Clock 4.096 MHz.
This output is a 4.096 MHz clock used for ST-BUS operation.
C2o
(CMOS) O
17
Clock 2.048 MHz.
This output is a 2.048 MHz clock used for ST-BUS operation.
C3o
(CMOS) O
16
Clock 3.088 MHz.
This output is a 3.088 MHz clock used for T1 applications.
C1.5o
(CMOS) O
15
Clock 1.544 MHz.
This output is a 1.544 MHz clock used for T1 applications.
C6o
(CMOS) O
14
Clock 6.312 MHz.
This output is a 6.312 MHz clock used for DS2 applications.
F32o
(CMOS) O
40
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 31 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 8.192 Mb/s.
F16o
(CMOS) O
39
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 8.192 Mb/s.
F8o
(CMOS) O
36
Frame Pulse.
This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame.
F0o
(CMOS) O
33
Frame Pulse ST-BUS 2.048 Mb/s.
This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s.
RSP
(CMOS) O
41
Receive Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
to connect to Siemens MUNICH-32 device.
TSP
(CMOS) O
42
Transmit Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
to connect to Siemens MUNICH-32 device.
TDO
(CMOS) O
29
Test Serial Data Out.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state if JTAG scan is
not enabled.
TDI
I
32
Test Serial Data In.
JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDDD.
TRST
I30
Test Reset.
Asynchronously initializes the JTAG TAP controller by putting it in Test-Logic-Reset state. This pin is internally pulled up to
VDDD. It is connected to the ground for normal applications.
TCK
I
28
Test Clock.
Provides a clock to JTAG test logic.
TMS
I
31
Test Mode Select.
JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDDD.
IC0, IC1, IC2
-
53, 54, 55
Internal Connection.
Internal Use. These pins should be connected to VSS when in normal operation.
Table - 1 Pin Description (Continued)
Name
Type
Pin
Number
Description
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