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參數(shù)資料
| 型號(hào)： | IDT82V3001APVG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN W/SGL REF INP 56-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | WAN |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 32.768MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V3001APVG8 |
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MEASURES OF PERFORMANCE
18
October 15, 2008
IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
observation period is usually the time from the disturbance, to just after
the synchronizer has settled to a steady state.
In the case of the IDT82V3001A, the output signal phase continuity is
maintained to within ±5 ns at the instance (over one frame) of all mode
changes. The total phase shift, depending on the type of mode change,
may accumulate up to 200 ns over many frames. The rate of change of
the 200 ns phase shift is limited to a maximum phase slope of
approximately 5 ns/125 s. This meets AT&T TR62411 maximum phase
slope requirement of 7.6 ns/125 s and Telcordia GR-1244-CORE (81
ns/1.326 ms).
4.12
PHASE LOCK TIME
This is the time it takes the synchronizer to phase lock to the input
signal. Phase lock occurs when the input signal and output signal are
not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many
factors, which include:
i) Initial input to output phase difference
ii) Initial input to output frequency difference
iii) Synchronizer loop filter
iv) Synchronizer limiter
Although a short lock time is desirable, it is not always possible to
achieve due to other synchronizer requirements. For instance, better
jitter transfer performance is achieved with a lower frequency loop filter
which increases lock time. And better (smaller) phase slope
performance (limiter) results in longer lock times. The IDT82V3001A
loop filter and limiter were optimized to meet AT&T TR62411 jitter
transfer and phase slope requirements. Consequently, phase lock time,
which is not a standards requirement, may be longer than in other
applications. See Table - 7 for Maximum Phase Lock Time.
The IDT82V3001A provides a fast lock pin (FLOCK), which enables
the DPLL to lock to an incoming reference within approximately 500 ms
when set high.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3002A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A-01PVG | 功能描述:IC PLL WAN T1/E1 56SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3002A-01PVG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN T1/E1 56SSOP |
| IDT82V3002APV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
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