參數(shù)資料
型號(hào)： IDT82V2608BBG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 4/98頁(yè)
文件大?。?/td> 0K
描述： IC INVERSE MUX 8CH ATM 208-BGA
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 無(wú)線
接口： Utopia
電源電壓： 2.97 V ~ 3.63 V
封裝/外殼： 208-BGA
供應(yīng)商設(shè)備封裝： 208-PBGA（17x17）
包裝： 托盤(pán)
安裝類型： 表面貼裝
其它名稱： 82V2608BBG
PIN DESCRIPTION
12
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
2
PIN DESCRIPTION
Table-1 Pin Description
Name
Pin Number
Input/Output
Description
Global Signals
SYSCLK
E4
I
SYSCLK: System Clock
System clock for the IDT82V2608. Default is 20 MHz.
RST
R11
I
RST: System Reset
System reset signal, low active. After reset, all registers are reset to default values, and both the con-
tents in SRAM and the downloaded software are cleared.
ATM Utopia Interface
TxClk
E14
I
TxClk: Utopia Transmit Clock
Utopia transmit clock used to transfer data from the ATM layer to the IDT82V2608. The frequency of
the TxClk should be less than or equal to that of the system clock.
Data is sampled on the rising edge of this signal.
TxEnb
G14
I
TxEnb: Utopia Transmit Enable
Utopia low active signal asserted by the ATM layer device during cycles when TxData contains valid
cell data.
The TxEnb input is sampled on the rising edge of TxClk.
TxAddr4
TxAddr3
TxAddr2
TxAddr1
TxAddr0
F15
F14
F13
E16
E15
I
TxAddr[4:0]: Utopia Transmit Address
Utopia transmit port address driven from the ATM layer to poll and select an appropriate port.
The TxAddr[4:0] input bus are sampled on the rising edge of TxClk.
TxData7
TxData6
TxData5
TxData4
TxData3
TxData2
TxData1
TxData0
G15
G16
H14
H15
H16
J16
J15
J14
I
TxData[7:0]: Utopia Transmit Data
Utopia 8-bit data bus driven from the ATM layer to the IDT82V2608.
The TxData[7:0] input bus are sampled on the rising edge of TxClk.
TxClav
E13
High-Z
O
TxClav: Utopia Transmit Cell Available
Utopia transmit cell available signal from the IDT82V2608 to the ATM layer. A polled port drives TxClav
only during each cycle following one with its address on the TxAddr lines. The polled port asserts
TxClav high to indicate its corresponding FIFO can accept the transfer of a complete cell, otherwise it
deasserts the signal.
The TxClav output is updated on the rising edge of TxClk.
Note: This pin requires a pull-down resistor.
TxSOC
F16
I
TxSOC: Utopia Transmit Start of Cell
Utopia start of cell signal. It will be driven high by the ATM layer when TxData[7:0] contain the first valid
byte of a cell.
The TxSOC input is sampled on the rising edge of TxClk.
RxClk
D16
I
RxClk: Utopia Receive Clock
Utopia receive clock. The frequency of RxClk should be less than or equal to the frequency of the sys-
tem clock.
Data is sampled on the rising edge of this signal.
RxEnb
D15
I
RxEnb: Utopia Receive Enable
When this pin is low, the received data will be transferred on RxData[7:0] in the following cycles.
The RxEnb input is sampled on the rising edge of RxClk.
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