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參數(shù)資料
| 型號： | IDT82V2608BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 16/98頁 |
| 文件大小： | 0K |
| 描述： | IC INVERSE MUX 8CH ATM 208-BGA |
| 標準包裝： | 1 |
| 應用： | 無線 |
| 接口： | Utopia |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 封裝/外殼： | 208-BGA |
| 供應商設備封裝： | 208-PBGA（17x17） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | 82V2608BBG |
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INTERFACE
23
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
Channelized Non-Multi-Rate E1
In this mode, the system provides 2.048 MHz clock and 8 kHz frame
pulse for E1 bit stream exchange between the IDT82V2608 and the line
interface. The E1 time slot 0 is not used for data exchange while time
slot 16 may or may not be used for data exchange, depending on
Signalling or Non-Signalling mode.
Signalling and Non-Signalling
In signalling mode, time slot 0 and time slot 16 are not used for data
exchange between the IDT82V2608 and the line interface. In non-
signalling mode, only time slot 0 is not used for data exchange.
3.2.1.7 Mode14~Mode15
The multi-rate concept is defined in Multi-rate on page 22, and the
signalling and non-signalling concepts are defined in Signalling and
Non-Signalling on page 23. The system provides 8.192 MHz common
clock and 8 kHz common frame pulse.
In these modes, only the TSCCK and RSCCK pins are used to input
the 8.192 MHz clock in Tx and Rx directions respectively, and TSCFS
and RSCFS are used as common frame pulse in Tx and Rx directions
respectively. The TSCK[i], TSF[i], RSCK[i] and RSF[i] pins are not used
and should be connected to ground. The unused RSD pins should also
be connected to ground.
The data pins used for multiplexing are shown in Table-3.
3.2.2
LINE INTERFACE TIMING CLOCK MODES
Two timing clock modes can be selected. One is Common Clock
Mode, the other is Independent Clock Mode. The timing clock mode can
be individually configured for each link. In IMA mode, AddTxLink
command and AddRxLink command can be used to configure the clock
mode in the transmit and receive directions respectively. In UNI mode,
ConfigUNILink command can be used to configure the clock mode.
If a link is configured in Common Clock Mode, TSCCK and RSCCK
are used as Tx clock and Rx clock respectively, and TSCFS and RSCFS
are used as common frame pulse in Tx and Rx directions respectively.
If a link is configured in Independent Clock Mode, TSCK[i] and
RSCK[i] are used as Tx clock and Rx clock respectively, and TSF[i] and
RSF[i] are used as the frame pulse in Tx and Rx directions respectively.
These two timing clock modes can be configured at the same time,
i.e., some links can work in Common Clock Mode while other links can
work in Independent Clock Mode.
The line interface mode7~mode10 and mode14~mode15 cannot be
used in Independent Clock Mode.
3.2.3
LINE INTERFACE LOOPBACK FUNCTION
The line interface supports two line loopback functions, one is
external loopback mode and the other is internal loopback mode. The
two loopback modes can be selected by ConfigLoopMode command.
In external loopback mode, all the data received at the line side is
looped back to the transmit side and is transmitted out. When this func-
tion is enabled, all the links will be in external loopback mode. Data will
not be transmitted to the Utopia interface.
In internal loopback mode, the data transmitted are also sent to the
receive side. When this function is enabled, all the links will be in internal
loopback mode. Data will not be transmitted to the FE Utopia interface.
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