參數(shù)資料
型號(hào): IDT82V2608BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 20/98頁
文件大?。?/td> 0K
描述: IC INVERSE MUX 8CH ATM 208-BGA
標(biāo)準(zhǔn)包裝: 1
應(yīng)用: 無線
接口: Utopia
電源電壓: 2.97 V ~ 3.63 V
封裝/外殼: 208-BGA
供應(yīng)商設(shè)備封裝: 208-PBGA(17x17)
包裝: 托盤
安裝類型: 表面貼裝
其它名稱: 82V2608BBG
INTERFACE
27
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
3.3.6
PROCEDURE OF LOADING SOFTWARE AND SENDING
COMMANDS
After chip reset, the IMAOS08 or IMAOS08_Slave (a binary file
shipped with the chip) should be loaded to the IDT82V2608 to interpret
commands. The procedure of loading the IMAOS08 or IMAOS08_Slave
is the same with that of sending the commands. Figure-8 shows the
Input-FIFO write process and Figure-9 shows the Output-FIFO read
process.
Figure-8 Input FIFO Write Process
Table-13 Input FIFO Internal State Register (INPUT_FIFO_INTERNAL_STATE_REG)
(R, Address=08H)
Symbol
Position
Default
Description
-
7-5
0
Reserved.
Input_remain_msg_length[4:0]
4-0
0
The length of the message remaining in the Input FIFO to be processed by the IDT82V2608.
write_message(char *message,char L)
{
wait(INPUT_FIFO_EMPTY_STATE_EVENT);
write_reg(FIFO_INT_RESET_REG,0x02);
for(i=0;i<L;i++)
{
write_reg(INPUT_FIFO_DATA_REG,message[i]);
}
write_reg(INPUT_FIFO_LENGTH_REG,L);
}
Input_FIFO_empty_state
bit is set?
Read Input_FIFO_empty_state bit of
FIFO_STATE_REGregister
Write L(L<=16) bytesinto Input_FIFO
Write value L into
INPUT_FIFO_LENGTH_REG register
N
Y
InputFIFOWriteProcess
Clearthe Input_FIFO_empty_state bit
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