參數(shù)資料
型號： IDT82V2088DR
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 6/78頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 8CH 208-TQFP
標(biāo)準(zhǔn)包裝： 12
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
包裝： 托盤
其它名稱： 82V2088DR
14
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
SCLKE
Input
11
B1
SCLKE: Serial Clock Edge Select
Signal on this pin determines the active edge of SCLK to output SDO. The active clock edge is selected
as shown below:
JTAG Signals
TRST
Input
Pullup
204
A6
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resis-
tor. To ensure deterministic operation of the test logic, TMS should be held high while the signal applied
to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
TMS
Input
Pullup
205
B6
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edges of TCK.TMS
has an internal pullup resistor.
TCK
Input
208
A10
TCK: JTAG Test Clock
This pin is the input clock for JTAG. The data on TDI and TMS is clocked into the device on the rising
edges of TCK while the data on TDO is clocked out of the device on the falling edges of TCK. When
TCK is idle at a low level, all stored-state devices contained in the test logic will retain their state indef-
initely.
TDO
Output
207
B10
TDO: JTAG Test Data Output
This output pin is in high impedance state normally and is used for reading all the serial configuration
and test data from the test logic. The data on TDO is clocked out of the device on the falling edges of
TCK.
TDI
Input
Pullup
206
D13
TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pullup resistor.
The data on TDI is clocked into the device on the rising edges of TCK.
Power Supplies and Grounds
VDDIO
-
22, 33
103, 128
158
G9, G10
H1, K1
K16
3.3V I/O Power Supply
GNDIO
-
20, 35
104, 130
157
H4, J9
J10, J13, K4
I/O Ground
VDDT1
VDDT2
VDDT3
VDDT4
VDDT5
VDDT6
VDDT7
VDDT8
-
161, 162
179, 180
181, 182
199, 200
61, 62
79, 80
81, 82
99, 100
A14, B14
A9, B9
C9, D9
A4, B4
R4, T4
N9, P9
R9, T9
R14, T14
3.3V Power Supply for Transmitter Driver
GNDT1
GNDT2
GNDT3
GNDT4
GNDT5
GNDT6
GNDT7
GNDT8
-
165, 166
175, 176
185, 186
195,196
65, 66
75, 76
85, 86
95, 96
A12, B12
A7, B7
C7, D7
A2, B2
R2, T2
N7, P7
R7, T7
R12, T12
Analog Ground for Transmitter Driver
VDDA
-
60, 201
C1, T10
3.3V Analog Core Power Supply
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
PQFP208
PBGA208
SCLKE
SCLK
Low
Rising edge is the active edge
High
Falling edge is the active edge
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