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參數(shù)資料
| 型號： | IDT82V2088DR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 38/78頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 8CH 208-TQFP |
| 標(biāo)準(zhǔn)包裝： | 12 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2088DR |
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43
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4.2.4
RECEIVE PATH CONTROL REGISTERS
Table-35 TCF3: Transmitter Configuration Register 3
(R/W, Address = 05H,25H,45H,65H,85H,A5H,C5H,E5H)
Symbol
Bit
Default
Description
DONE
7
0
After ‘1’ is written to this bit, a read or write operation is implemented.
RW
6
0
This bit selects read or write operation
= 0: write to RAM
= 1: read from RAM
UI[1:0]
5-4
00
These bits specify the unit interval address. There are 4 unit intervals.
= 00: UI address is 0 (The most left UI)
= 01: UI address is 1
= 10: UI address is 2
= 11: UI address is 3
SAMP[3:0]
3-0
0000
These bits specify the sample address. Each UI has 16 samples.
= 0000: sample address is 0 (The most left Sample)
= 0001: sample address is 1
= 0010: sample address is 2
......
= 1110: sample address is 14
= 1111: sample address is 15
Table-36 TCF4: Transmitter Configuration Register 4
(R/W, Address = 06H,26H,46H,66H,86H,A6H,C6H,E6H)
Symbol
Bit
Default
Description
-7
0
Reserved
WDAT[6:0]
6-0
0000000
In Indirect Write operation, the WDAT[6:0] will be loaded to the pulse template RAM, specifying the amplitude of
the Sample.
After an Indirect Read operation, the amplitude data of the Sample in the pulse template RAM will be output to the
WDAT[6:0].
Table-37 RCF0: Receiver Configuration Register 0
(R/W, Address = 07H,27H,47H,67H,87H,A7H,C7H,E7H)
Symbol
Bit
Default
Description
-
7-5
000
Reserved
R_OFF
4
0
Receiver power down enable
= 0: Receiver power up
= 1: Receiver power down
RD_INV
3
0
Receive data invert
= 0: data on RDn or RDPn/RDNn is active high
= 1: data on RDn or RDPn/RDNn is active low
RCLK_SEL
2
0
Receive clock edge select (this bit is ignored in slicer mode)
= 0: data on RDn or RDPn/RDNn is updated on the rising edges of RCLKn
= 1: data on RDn or RDPn/RDNn is updated on the falling edges of RCLKn
R_MD[1:0]
1-0
00
Receiver path decoding selection
= 00: receive data is HDB3 (E1) / B8ZS (T1/J1) decoded and output on RDn with single rail NRZ format
= 01: receive data is AMI decoded and output on RDn with single rail NRZ format
= 10: decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with
clock recovery)
= 11: both CDR and decoder blocks are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
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