參數(shù)資料
型號: IDT82V2088DR
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 4/78頁
文件大?。?/td> 0K
描述: IC LIU T1/J1/E1 8CH 208-TQFP
標準包裝: 12
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: 82V2088DR
12
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
MCLK
Input
17
G1
MCLK: Master Clock
MCLK is an independent, free-running reference clock. It is a single reference for all operation modes
and provides selectable1.544 MHz or 37.056 MHz for T1/J1 operating mode while 2.048 MHz or
49.152 MHz for E1 operating mode.
The reference clock is used to generate several internal reference signals:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLKn signal during a loss of signal condition.
Reference clock during Transmit All Ones (TAO) and all zeros condition. When sending PRBS/
QRSS or Inband Loopback code, either MCLK or TCLKn can be selected as the reference clock.
Reference clock for ATAO and AIS.
The loss of MCLK will turn all the eight TTIP/TRING into high impedance status.
MCLKS
Input
56
R6
MCLKS: Master Clock Select
If 2.048 MHz (E1) or 1.544 MHz (T1/J1) is selected as the MCLK, this pin should be connected to
ground; and if the 49.152 MHz (E1) or 37.056 MHz (T1/J1) is selected as the MCLK, this pin should
be pulled high.
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
LOS8
Output
1
3
4
5
6
7
8
9
C2
C3
D1
D2
D3
E1
E2
E3
LOSn: Loss of Signal Output for Channel 1~8
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates
the loss of received signals in channel n. The LOSn pin will become low automatically when valid
received signal is detected again. The criteria of loss of signal are described in 3.5 LOS AND AIS
Control Interface
P/S
Input
14
G4
P/S: Parallel or Serial Control Interface Select
Level on this pin determines which control mode is selected to control the device as follows:
The serial microcontroller interface consists of CS, SCLK, SDI, SDO and SCLKE pins. Parallel micro-
controller interface consists of CS, A[7:0], D[7:0], DS/RD, R/W/WR pins. The device supports non-mul-
tiplexed parallel interfaces as follows:
INT/MOT
Input
12
F2
INT/MOT: Intel or Motorola Microcontroller Interface Select
In microcontroller mode, the parallel microcontroller interface is configured for Motorola compatible
microcontrollers when this pin is low, or for Intel compatible microcontrollers when this pin is high.
CS
Input
45
N1
CS: Chip Select
In serial and parallel microcontroller mode, this pin is asserted low by the microcontroller to enable
microcontroller interface. For each read or write operation, this pin must be changed from high to low,
and will remain low until the operation is over.
SCLK
Input
46
N2
SCLK: Shift Clock
In serial microcontroller interface mode, signal on this pin is the shift clock for the serial interface. Con-
figuration data on pin SDI is sampled on the rising edges of SCLK. Configuration and status data on
pin SDO is clocked out of the device on the rising edges of SCLK if pin SCLKE is low, or on the falling
edges of SCLK if pin SCLKE is high.
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
PQFP208
PBGA208
P/S
Control Interface
High
Parallel Microcontroller Interface
Low
Serial Microcontroller Interface
P/S, INT/MOT
Microcontroller Interface
10
Motorola non-multiplexed
11
Intel non-multiplexed
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