參數(shù)資料
型號: IDT82V2051EPPG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 4/61頁
文件大小: 0K
描述: IC LIU E1 SGL SHORT HAUL 44-TQFP
標(biāo)準(zhǔn)包裝: 1,250
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 82V2051EPPG8
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Pin Description
12
December 9, 2005
SDO
ACK
RDY
TERM
O
I
23
SDO: Serial Data Output
In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at SDO
pin is clocked out of the device on the falling edge of SCLK if SCLKE pin is high, or on the rising edge of SCLK if SCLKE pin
is low.
ACK: Acknowledge Output
In Motorola parallel mode interface, the low level on this pin means:
The valid information is on the data bus during a read operation.
The write data has been accepted during a write cycle.
RDY: Ready signal output
In Intel parallel mode interface, the low level on this pin means a read or write operation is in progress; a high acknowledges
a read or write operation has been completed.
TERM: Internal or external termination select in hardware mode
This pin selects internal or external impedance matching for both receiver and transmitter.
0 = ternary interface with external impedance matching network
1 = ternary interface with internal impedance matching network
SCLKE
RD
DS
MONT
I
22
SCLKE: Serial Clock Edge Select
In serial microcontroller interface mode, this signal selects the active edge of SCLK for outputting SDO. The output data is valid
after some delay from the active clock edge. It can be sampled on the opposite edge of the clock. The active clock edge which
clocks the data out of the device is selected as shown below:
RD: Read Strobe
In Intel parallel multiplexed interface mode, the data is driven to AD[7:0] by the device during low level of RD in a read operation.
DS: Data Strobe
In Motorola parallel multiplexed interface mode, this signal is the data strobe of the parallel interface. In a write operation (R/
W = 0), the data on AD[7:0] is sampled into the device. In a read operation (R/W = 1), the data is driven to AD[7:0] by the device.
MONT: Receive Monitor gain select
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0 dB
1= 26 dB
AD7
I/O
33
AD7: Address/Data Bus bit7
In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller
interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 k
resistor.
In Hardware mode, this pin has to be tied to GND.
AD6
I/O
32
AD6: Address/Data Bus bit6
In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller
interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 k
resistor.
In Hardware mode, this pin has to be tied to GND.
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
SCLKE
SCLK
Low
Rising edge is the active edge.
High
Falling edge is the active edge.
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