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參數(shù)資料
| 型號： | IDT82V2051EPPG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1 SGL SHORT HAUL 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V2051EPPG8 |
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IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Functional Description
22
December 9, 2005
3.4.2
JITTER ATTENUATOR PERFORMANCE
The performance of the Jitter Attenuator in the IDT82V2051E meets the
ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011 and ETSI
TBR12/13 specifications. Details of the Jitter Attenuator performance is
3.5
LOS AND AIS DETECTION
3.5.1
LOS DETECTION
The Loss of Signal Detector monitors the amplitude of the incoming sig-
nal level and pulse density of the received signal on RTIP and RRING.
LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0DH). LOS will be
declared by pulling LOS pin to high (LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
NotethatLOSindicationisnotsupportedifthedeviceisoperatedinLine
Monitor Mode. Refer to 3.3.2 Line Monitor.
LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT0, 0DH).
LOS status is cleared by pulling LOS pin to low.
Figure-10 LOS Declare and Clear
LOS detect level threshold
With the Adaptive Equalizer off, the amplitude threshold Q is fixed on
800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hys-
teresis).
With the Adaptive Equalizer on, the value of Q can be selected by
LOS[4:0] bit (RCF1, 0BH), while P=Q+4 dB (4 dB is the LOS level detect
hysteresis). Refer to Table-20 TCF1: Transmitter Configuration Register 1
for LOS[4:0] bit values available.
When the chip is configured by hardware, the Adaptive Equalizer can
not be enabled and Programmable LOS levels are not available (pin 29 has
to be set to ‘0’).
Criteria for declare and clear of a LOS detect
The detection supports G.775 and ETSI 300233/I.431. The criteria can
be selected by LAC bit (MAINT0, 0DH).
with and without the Adaptive Equalizer enabled.
All Ones output during LOS
On the system side, the RDP/RDN will reflect the input pulse “transition”
at the RTIP/RRING side and output recovered clock (but the quality of the
output clock can not be guaranteed when the input level is lower than the
maximum receive sensitivity) when AISE bit (MAINT0, 0DH) is 0; or output
All Ones as AIS when AISE bit (MAINT0, 0DH) is 1. In this case, RCLK out-
put is replaced by MCLK.
Onthelineside,theTTIP/TRINGwilloutputAllOnesasAISwhenATAO
bit (MAINT0, 0DH) is 1. The All Ones pattern uses MCLK as the reference
clock.
LOS indicator is always active for all kinds of loopback modes.
Table-6 Criteria of Starting Speed Adjustment
FIFO Depth
Criteria for Adjusting Data Outgoing Speed
32 Bits
2 bits close to its full or emptiness
64 Bits
3 bits close to its full or emptiness
128 Bits
4 bits close to its full or emptiness
signal level<Q
(observing windows= N)
(observing windows= M)
signal level>P
density=OK
LOS=1
LOS=0
Table-7 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled
Control bit (LAC)
LOS declare threshold
LOS clear threshold
0 = G.775
Level < 800 mVpp; N=32 bits
Level > 1 Vpp; M=32 bits; 12.5% mark density; <16 consecutive zeroes
1 = I.431/ETSI
Level < 800 mVpp; N=2048 bits
Level > 1 Vpp; M=32 bits; 12.5% mark density; <16 consecutive zeroes
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| IDT82V2052E | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2052EPF | 功能描述:IC LIU E1 2CH SHORT HAUL 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2052EPF8 | 功能描述:IC LIU E1 2CH SHORT HAUL 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2052EPFG | 功能描述:IC LIU E1 2CH SHORT HAUL 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2052EPFG8 | 功能描述:IC LIU E1 2CH SHORT HAUL 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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