參數(shù)資料
型號： IDT82V2042EPFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 55/83頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 2CH SHORT 80TQFP
標(biāo)準(zhǔn)包裝： 750
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 82V2042EPFG8
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
HARDWARE CONTROL PIN SUMMARY
59
December 12, 2005
5
HARDWARE CONTROL PIN SUMMARY
Table-51 Hardware Control Pin Summary
Pin No.
TQFP
Symbol
Description
9
10
MODE1
MODE0
MODE[1:0]: Operation mode of Control interface select (global control)
00= Hardware interface
01= Serial interface
10= Parallel - non-Multiplexed - Motorola Interface
11= Parallel - non-Multiplexed - Intel Interface
13
12
TERM1
TERM2
TERMn: Termination interface select (per channel control)
These pins select internal or external impedance matching for channel n (n=1 or 2)
0 = ternary interface with internal impedance matching network.
1 = ternary interface with external impedance matching network in E1 mode; ternary interface with external impedance matching
network for receiver and ternary interface with internal impedance matching network for transmitter in T1/J1 mode. (External imped-
ance matching is not supported by T1/J1 mode transmitter.)
(This applies to ZB die revision only).
14
15
RXTXM1
RXTXM0
RXTXM[1:0]: Receive and transmit path operation mode select (global control)
00= single rail with HDB3/B8ZS coding
01= single rail with AMI coding
10= dual rail interface with CDR enable
11= slicer mode
54
53
52
51
50
49
48
47
PULS13
PULS12
PULS11
PULS10
PULS23
PULS22
PULS21
PULS20
PULSn[3:0]: These pins are used to select the following functions (per channel control):
T1/E1/J1 mode (T1/E1/J1 selection of common clock is decided by PULS1n/PULS2n, n=0~3)
Transmit pulse template
Internal termination impedance (75
/100/110/120)
PULSn[3:0]
T1/E1/J1
TCLK
Cable impedance
(internal matching impedance)
Cable range
Cable loss
0000
E1
2.048 MHz
75
-0-24 dB
0001
E1
2.048 MHz
120
-0-24 dB
0010
DSX1
1.544 MHz
100
0-133 ft
0-0.6 dB
0011
DSX1
1.544 MHz
100
133-266 ft
0.6-1.2 dB
0100
DSX1
1.544 MHz
100
266-399 ft
1.2-1.8 dB
0101
DSX1
1.544 MHz
100
399-533 ft
1.8-2.4 dB
0110
DSX1
1.544 MHz
100
533-655 ft
2.4-3.0 dB
0111
J1
1.544 MHz
110
0-655 ft
0-3.0 dB
1000 - 1111
Reserved
57
59
RPD1
RPD2
RPDn: Receiver power down control (per channel control)
0= Normal operation
1= receiver power down
46
45
56
55
PATT11
PATT10
PATT21
PATT20
PATTn[1:0]: Transmit test pattern select (per channel control)
In hardware control mode, these pins select the transmit pattern for channel n (n=1 or 2)
00 = normal
01= All Ones
10= PRBS
11= transmitter power down
16
17
JA1
JA0
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select (global control)
00= JA is disabled
01= JA in receiver, broad bandwidth, FIFO=64 bits
10= JA in receiver, narrow bandwidth, FIFO=128 bits
11= JA in transmitter, narrow bandwidth, FIFO=128 bits
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