參數(shù)資料
型號: IDT82V2042EPFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 50/83頁
文件大?。?/td> 0K
描述: IC LIU T1/J1/E1 2CH SHORT 80TQFP
標準包裝: 750
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設備封裝: 80-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V2042EPFG8
IDT82V2042E
DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION
54
December 12, 2005
Table-44 INTES: Interrupt Trigger Edge Select Register
(R/W, Address = 15H, 35H)
Symbol
Bit
Default
Description
-7
0
Reserved
IBLBA_IES
6
0
This bit determines the Inband Loopback Activate Code interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBA_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBA_S bit in STAT0
status register
IBLBD_IES
5
0
This bit determines the Inband Loopback Deactivate Code interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBD_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBD_S bit in STAT0
status register
PRBS_IES
4
0
This bit determines the PRBS/QRSS synchronization status interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the PRBS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in STAT0
status register
TCLK_IES
3
0
This bit determines the TCLK Loss interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in STAT0
status register
DF_IES
2
0
This bit determines the Driver Failure interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the DF_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in STAT0 status
register
AIS_IES
1
0
This bit determines the AIS interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the AIS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in STAT0 status
register
LOS_IES
0
This bit determines the LOS interrupt event.
= 0: Interrupt is generated as a ‘0’ to ‘1’ transition of the LOS_S bit in STAT0 status register
= 1: Interrupt is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in STAT0 status
register
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