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| 型號： | IDT82V2041EPP |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 26/75頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 1CH 44-TQFP |
| 標準包裝： | 80 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2041EPP |
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IDT82V2041E
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Functional Description
32
December 9, 2005
3.9
ERROR DETECTION/COUNTING AND INSERTION
3.9.1
DEFINITION OF LINE CODING ERROR
The following line encoding errors can be detected and counted by the
IDT82V2041E:
Received Bipolar Violation (BPV) Error: In AMI coding, when two
consecutive pulses of the same polarity are received, a BPV error
is declared.
HDB3/B8ZS Code Violation (CV) Error: In HDB3/B8ZS coding, a
CV error is declared when two consecutive BPV errors are
detected, and the pulses that have the same polarity as the previ-
ous pulse are not the HDB3/B8ZS zero substitution pulses.
Excess Zero (EXZ) Error: There are two standards defining the
EXZ errors: ANSI and FCC. The EXZ_DEF bit (MAINT6, 13H)
chooses which standard will be adopted by the chip to judge the
EXZ error. Table-17 shows definition of EXZ. In hardware control
mode, only ANSI standard is adopted.
3.9.2
ERROR DETECTION AND COUNTING
Which type of the receiving errors (Received CV/BPV errors, excess
zero errors and PRBS logic errors) will be counted is determined by
ERR_SEL[1:0] bits (MAINT6, 13H). Only one type of receiving error can be
counted at a time except that when the ERR_SEL[1:0] bits are set to ‘11’,
both CV/BPV and EXZ errors will be detected and counted.
Theselectedtypeofreceivingerrorsiscountedinaninternal16-bitError
Counter. Once an error is detected, an error interrupt which is indicated by
corresponding bit in (INTS1, 1AH) will be generated if it is not masked. This
Error Counter can be operated in two modes: Auto Report Mode and Man-
ual Report Mode, as selected by the CNT_MD bit (MAINT6, 13H). In Single
Rail mode, once BPV or CV errors are detected, the CV pin will be driven
to high for one RCLK period.
Auto Report Mode
In Auto Report Mode, the internal counter starts to count the received
errorswhentheCNT_MDbit(MAINT6,13H)issetto‘1’.Aone-secondtimer
is used to set the counting period. The received errors are counted within
one second. If the one-second timer expires, the value in the internal
counter will be transferred to (CNT0, 1BH) and (CNT1, 1CH), then the inter-
nal counter will be reset and start to count received errors for the next sec-
ond. The errors occurred during the transfer will be accumulated to the next
round. The expiration of the one-second timer will set TMOV_IS bit (INTS1,
1AH) to ‘1’, and will generate an interrupt if the TIMER_IM bit (INTM1, 15H)
is set to‘0’.The TMOV_IS bit (INTS1, 1AH) will becleared after the interrupt
register is read. The content in the (CNT0, 1BH) and (CNT1, 1CH) should
be read within the next second. If the counter overflows, a counter overflow
interrupt which is indicated by CNT_OV_IS bit (INTS1, 1AH) will be gener-
ated if it is not masked by CNT_IM bit (INTM1, 15H).
Figure-16 Auto Report Mode
Table-17 EXZ Definition
EXZ Definition
ANSI
FCC
AMI
More than 15 consecutive 0s are detected
More than 80 consecutive 0s are detected
HDB3
More than 3 consecutive 0s are detected
B8ZS
More than 7 consecutive 0s are detected
One-Second Timer expired?
counting
Auto Report Mode
(CNT_MD=1)
Bit TMOV_IS is set to '1'
Y
N
CNT0, CNT1
data in counter
counter
0
read the data in CNT0, CNT1 within
the next second
next second
repeats the
same process
Bit TMOV_IS is cleared after
the interrupt register is read
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