參數(shù)資料
型號： IDT82V2041EPP
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 16/75頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 1CH 44-TQFP
標(biāo)準(zhǔn)包裝： 80
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
其它名稱： 82V2041EPP
IDT82V2041E
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Functional Description
23
December 9, 2005
3.4.3
ADAPTIVE EQUALIZER
The Adaptive Equalizer can be enabled to increase the receive sensi-
tivity and to allow programming of the LOS level up to -24 dB. See3.6 Los
And AIS Detection. It can be enabled or disabled by setting EQ_ON bit to
‘1’ or ‘0’ (RCF1, 0BH).
3.4.4
RECEIVE SENSITIVITY
The Receive Sensitivity for both E1 and T1/J1 is -10 dB. With the Adap-
tive Equalizer enabled, the receive sensitivity will be -20 dB.
In Hardware mode, the Adaptive Equalizer can not be enabled and the
receive sensitivity is fixed at -10 dB for both E1 and T1/J1. Refer to 5 Hard-
3.4.5
DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be40%,50%,60%or70%,asselectedbytheSLICE[1:0]bits(RCF2,0CH).
The output of the Data Slicer is forwarded to the CDR (Clock & Data Recov-
ery) unit or to the RDP/RDN pins directly if the CDR is disabled.
3.4.6
CDR (CLOCK & DATA RECOVERY)
The CDR is used to recover the clock and data from the received signal.
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDP/RDN pins directly.
3.4.7
DECODER
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 0AH) is used to select
the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0] bits
(RCF0, 0AH) are used to select the AMI decoder or HDB3 decoder.
When the chip is configured by hardware, the operation mode of receive
and transmit path can be selected by setting RXTXM1 and RXTXM0 pins.
Refer to 5 Hardware Control Pin Summary for details.
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