參數(shù)資料
型號(hào): IDT82P2521BHG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 105/147頁
文件大?。?/td> 0K
描述: IC LIU E1 21+1CH SHORT 640-PBGA
標(biāo)準(zhǔn)包裝: 5
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
其它名稱: 82P2521BHG
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Functional Description
60
December 7, 2005
3.5
CLOCK INPUTS AND OUTPUTS
The IDT82P2521 provides two kinds of clock outputs:
Free running clock outputs on CLKE1
Receiver clock outputs on REFA and REFB
- selected from any of the 22 recovered line clocks
- driven by MCLK (free running)
- driven by external CLKA/CLKB input
A Frequency Synthesizer is also available to scale REFA to 8
different frequencies.
The following Clock Inputs are provided:
MCLK as programmable reference timing for the IDT82P2521.
CLKA and CLKB as optional input clock source for REFA and
REFB respectively
3.5.1
FREE RUNNING CLOCK OUTPUTS ON CLKE1
An internal clock generator uses MCLK as reference to generate all
the clocks required by internal circuits and CLKE1 outputs. MCLK is a
stable jitter-free1 clock input with ±50 ppm accuracy. The clock
frequency of MCLK is 2.048 X N MHz (1
≤ N ≤ 8, N is an integer
number), as determined by MCKSEL[3:0]. Refer to Chapter 2 Pin
Description for details.
The outputs on CLKE1 is free running (locking to MCLK). The output
of CLKE1 is determined by the CLKE1_EN bit (b3, CLKG) and the
CLKE1 bit (b2, CLKG). Refer to Table-15.
1. Jitter is no more than 0.001 UI.
Table-15 Clock Output on CLKE1
Control Bits
Clock Output On CLKE1
CLKE1_EN
CLKE1
0
(don’t-care)
High-Z
1
08 KHz
1
2.048 KHz
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