參數(shù)資料
型號: IDT821054APF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 編解碼器
英文描述: QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
中文描述: A/MU-LAW, PCM CODEC, PQFP64
封裝: TQFP-64
文件頁數(shù): 16/42頁
文件大小: 512K
代理商: IDT821054APF
16
IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
tone coefficients, can only be addressed on a per-channel basis.
Therefore, users should specify a channel (by setting the corresponding
CE bit in GREG6 to ‘1’) before writing/reading tone coefficients to/from
the Coe-RAM.
To write a Coe-RAM word, 16 bits (b[15:0]) or two 8-bit bytes are
needed to fulfill with MSB first
,
but the lowest two bits (b[1:0]) will be
ignored. When read, each word will output 16 bits with MSB first, but the
lowest two bits (b[1:0]) are meaningless.
The address in a Coe-RAM command (b[4:0]) specifies a block of
Coe-RAM to be accessed. When a Coe-RAM command is executed, the
CODEC automatically counts down from the highest address to the
lowest address of the specified block. So all 8 words of the block will be
addressed by one Coe-RAM command.
When addressing the Coe-RAM, the procedure of consecutive
adjacent addressing can be stopped by the
CS
signal at any time. If the
CS
signal is changed from low to high, the operation to the current word
and the next adjacent words will be aborted. However, the previous
operation results will not be affected.
3.1.5
3.1.5.1
Writing to LREG2 and LREG1 of Channel 1:
1010, 0101
Channel Enable command
0001, 0010
Data for GREG6 (Channel 1 is enabled for programming)
1000, 0001
Local register write command (The address is '00001', which means that data will be written to LREG2 and LREG1.)
xxxx, xxxx
Data for LREG2
xxxx, xxxx
Data for LREG1
Reading from LREG2 and LREG1 of Channel 1:
1010, 0101
Channel Enable command
0001, 0010
Data for GREG6 (Channel 1 is enabled for programming)
0000, 0001
Local register read command (The address is '00001', which means that LREG2 and LREG1 will be read.)
After the preceding commands are executed, data will be sent out as follows:
1000, 0001
Identification code
xxxx, xxxx
Data read out from LREG2
xxxx, xxxx
Data read out from LREG1
3.1.5.2
Example of Programming Global Registers
Writing to GREG1:
1010, 0000
Global register write command (The address is '00000', which means that data will be written to GREG1.)
1111, 1111
Data for GREG1
Reading from GREG1:
0010, 0000
Global register read command (The address is '00000', which means that GREG1 will be read.)
After the preceding command is executed, data will be sent out as follows:
1000, 0001
Identification code
0000, 0001
Data read out from GREG1
3.1.5.3
Example of Programming the Coefficient-RAM
As described in
“3.1.4 Addressing the Coe-RAM”
, the Coe-RAM blocks used for containing the IMF, ECF, GIS, FRX, GTX, FRR and GRX
coefficients are shared by all four channels. When coefficients are written to these blocks, they will be used by all four channels. But the four words
(word 20 to 23), which contain the tone coefficients, can only be addressed on a per-channel basis. Therefore, users should specify a channel before
writing/reading tone coefficients to/from the Coe-RAM.
Writing to the Coe-RAM
Examples for Coe-RAM blocks shared by all four channels:
1110,0000
Coe-RAM write command (The address of '00000' is located in block 1, which means that data will be written to block 1.)
data byte 1
high byte of word 8 of block 1
data byte 2
low byte of word 8 of block 1
data byte 3
high byte of word 7 of block 1
data byte 4
low byte of word 7 of block 1
data byte 5
high byte of word 6 of block 1
data byte 6
low byte of word 6 of block 1
data byte 7
high byte of word 5 of block 1
data byte 8
low byte of word 5 of block 1
data byte 9
high byte of word 4 of block 1
data byte 10
low byte of word 4 of block 1
data byte 11
high byte of word 3 of block 1
data byte 12
low byte of word 3 of block 1
data byte 13
high byte of word 2 of block 1
PROGRAMMING EXAMPLES
Example of Programming Local Registers
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