參數(shù)資料
型號(hào)： IDT79RC32H435-300BCI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 53/53頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT CORE 300MHZ 256-BGA
標(biāo)準(zhǔn)包裝： 90
系列： Interprise™
處理器類型： MIPS32 32-位
速度： 300MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-CABGA（17x17）
包裝： 托盤(pán)
其它名稱： 79RC32H435-300BCI
9 of 53
January 19, 2006
IDT 79RC32435
EJTAG_TMS
I
EJTAG Mode. The value on this signal controls the test mode select of the
EJTAG Controller. When using the JTAG boundary scan, this pin should be left
disconnected (since there is an internal pull-up) or driven high.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary scan
logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external
pull-up on the board is recommended to meet the JTAG specification in cases
where the tester can access this signal. However, for systems running in func-
tional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high.
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data into or
out of the boundary scan logic, JTAG Controller, or the EJTAG Controller.
JTAG_TCK is independent of the system and the processor clock with a nomi-
nal 50% duty cycle.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary scan
logic, JTAG Controller, or the EJTAG Controller. When no data is being shifted
out, this signal is tri-stated.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic, JTAG
Controller, or the EJTAG Controller.
System
CLK
I
Master Clock. This is the master clock input. The processor frequency is a mul-
tiple of this clock frequency. This clock is used as the system clock for all mem-
ory and peripheral bus operations.
EXTBCV
I
Load External Boot Configuration Vector. When this pin is asserted (i.e.,
high) the boot configuration vector is loaded from an externally supplied value
during a cold reset. When this pin is negated, the boot configuration vector is
taken from the NVRAM located on-chip.
EXTCLK
O
External Clock. This clock is used for all memory and peripheral bus opera-
tions.
COLDRSTN
I
Cold Reset. The assertion of this signal initiates a cold reset. This causes the
processor state to be initialized, boot configuration to be loaded, and the internal
PLL to lock onto the master clock (CLK).
RSTN
I/O
Reset. The assertion of this bidirectional signal initiates a warm reset. This sig-
nal is asserted by the RC32435 during a warm reset.
Signal
Type
Name/Description
Table 1 Pin Description (Part 6 of 6)
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