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參數(shù)資料
| 型號(hào)： | IDT75T43100S50BS |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304 |
| 封裝： | 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 |
| 文件頁數(shù)： | 14/46頁 |
| 文件大小： | 446K |
| 代理商： | IDT75T43100S50BS |
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6.42
21
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Initialization
The IPC requires that the Reset signal (
RST) be active (Low) upon
powerupandremainlowuntilboththepowersuppliesandtheclocksignals
becomestable.Inaddition,atpowerup theJTAGReset(
TRST)pinmust
also be low. The IPC will respond to the
RST signal in both an
asynchronous and synchronous manner.
At Reset, the IPC will respond to the reset by asynchronously tri-
statingtheI/Opinsandoutputpins, which prevents bus contention from
occurring between IPC devices or the IPC and another device.
The IPC will come out of a reset condition synchronously. The IPC
requires the
RSTsignaltobeactive(Low)andtheCLK2XandPHASEN
signals be stable for thirty-two clock cycles to insure proper initialization.
The internal logic of the IPC is dependent on the clock to be present for
thedevicetobeinitialized. Thiswillaffectinternalstatemachinesandcertain
registers.
Initialization
A cold reset condition occurs whenever power is to be applied to the
IPC. In this case the IPC will have no defined data in either the Data or
Mask arrays. In addition the Depth Expansion Register, Global Mask
Registers, and Search Result Registers will also have undefined data.
ResethasnoaffectontheIdentificationandSizeRegisters.The registers
andData andMaskArraysareaffectedbyaColdResetasshowninTable
4.0.
Array / Register
Contents
Depth E xpans io n Re gister
Undefined
M us t be prog ram m e d
Data and M ask A rray s
Undefined
M us t be prog ram m e d
G lo b al M ask Re g iste rs
Reply W idth Regis ters
Undefined
M us t be prog ram m e d
S y ste m Co nfig uratio n Re g iste r
Undefined
M us t be prog ram m e d
S e arch Re sults Re g iste rs
Undefined
Identification Register
S ize Re g iste r
No t affe cte d
F5325 tb l 01a
Table 4.0 Condition after Cold Reset
Cold Reset
Ahotresetconditionoccurswhentheresetpinispulledlow,sometime
after the device had been in use and no power sequencing has taken
place. The
RST pin should be held low for ten clock cycles to complete
the proper re-initialization. In this case the data in the memory is not
corrupted. HoweverthestatestoredintheDepthExpansionRegisterand
SystemConfigurationRegister must bere-initialized. Thesetworegisters
willbeclearedduetotheapplicationoftheresetsignal. After
RSTpingoes
highwaitsixteenCLK2XcyclestoallowfortheDeviceExpansionRegister
tobere-configured,nextre-initializetheSystemConfigurationRegisterto
thedesiredstateandresumeoperation. The registersandData andMask
Arrays are affected by a Hot Reset as shown in Table 4.1.
Hot Reset
Table 4.1 Condition after Hot Reset
Array / Register
Contents
Depth E xpans io n Re gister
M us t b e Re -p ro g ram m e d
Data and M ask A rray s
No t affe c te d
G lo b al M ask Regis ters
Re ply W idth Registers
No t affe c te d
S ys te m Co nfig uratio n Re g iste r
A ll b its s e t to '0'
M us t b e Re -p ro g ram m e d
S e arch Re sults Regis ters
No t affe c te d
Id entification Register
S iz e Re gister
No t affe c te d
F5325 tb l 01b
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