參數(shù)資料
型號： IDT75T43100S50BS
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304
封裝： 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304
文件頁數(shù)： 11/46頁
文件大小： 446K
代理商： IDT75T43100S50BS
6.42
19
IDT75T43100
Preliminary Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Request Bus
SRR Select
Bit 20 Bit 19 Bit 18 Bit 17
00
0
SRR 0
00
0
1
SRR 1
00
1
0
SRR 2
00
1
SRR 3
01
0
SRR 4
01
0
1
SRR 5
01
1
0
SRR 6
01
1
SRR 7
X
All other bit combinations are reserved
E5325 tbl 11
Table 3.9 SRR Select
x
x Direct/Indirect
If“0”,indicatesthattheaddresstothe(Data/Mask)arraywillcomefrom
theAddressfieldoftheRequestDatabus. If“1”,indicatesthattheaddress
to the (Data/Mask) array will come from the Search Result Register as
specified in the SRR Select field of the Request Bus.
x
x SRR Select
ThisfieldisonlyusedforIndirectaddressing. ItspecifieswhichSearch
ResultRegisterwillbeusedtosupplytheaddresstothe(Data/Mask)array
as shown in Table 3.9.
x
x Address
This field specifies the address of the Access Type when using Direct
addressing (as specified by the Direct/Indirect bit). The address may be
used to access the (Data/Mask) array, external SRAM, or an internal IPC
register. The address decode map of the internal IPC registers is found
in Table 2.0.
Request Bus Format
Table 3.6 Device ID
Request Bus
IPC Device
Accessed
bit 33 bit 32 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26
00
0
00
0
1
00
1
0
2
00
11
3
00
0
1
00
4
00
0
1
0
1
5
00
0
1
0
6
00
0
1
11
7
11
111
1
All
X
XXX
XX
All other bit
combinations
are reserved
E5325 tbl 07
Request Bus
GMR Select for a Write Operation
Bit 23
Bit 22
00
GMR 10
01
GMR 11
10
GMR 12
11
No Masking
E5325 tbl 10
Table 3.7 Access Type
Table 3.8 GMR Select
Reques t B us
Acc e ss Ty p e
Bit 25
Bit 24
0
Inte rnal IP C Re g
0
1
Data A rray
1
0
M as k A rray
1
E xte rnal SRAM
E5325 tbl 08
x
x Access Type
There are four possible access types: a) Data array; b) Mask array; c)
SRAM; and, d) Register, as specified in Table 3.7.
x
x GMR Select
This field is only used to specify which of the three GMRs will be used
in a write operation. There are four possible options of GMRs to use for
a write operation, as shown in Table 3.8.
InaWriteoperation,theGMRselecteddefineswhichbitsinthearray
will be updated. For each bit in the selected GMR that is set to a “1”, data
from the Request Bus corresponding to this bit location will be written into
the array. For all other bits in the selected GMR that are a “0”, data in the
array corresponding to this bit location will remain unchanged.
x
x Device ID
This feature is needed when using multiple IPCs for depth expansion.
The Device ID is defined at power up and automatically assigned after
Reset. Table 3.6 shows which IPC is accessed using Device ID field. In
the case of a Read of all the IPC's, only IPC0 will drive the Request Bus.
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