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參數(shù)資料
| 型號(hào)： | IDT74LVC573AQ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O |
| 中文描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 0.635 MM PITCH, QSOP-20 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 71K |
| 代理商： | IDT74LVC573AQ |
INDUSTRIAL TEMPERATURE RANGE
2
IDT74LVC573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Max
Unit
V
°C
mA
mA
Termnal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
mA
ABSOLUTE MAX IMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
PIN CONFIGURATION
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
NOTE:
1. As applicable to the device type.
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
2
3
1
1
D
V
CC
16
15
14
5
Q
4
Q
6
Q
2
Q
1
Q
3
Q
11
8
Q
7
Q
LE
19
18
20
17
13
12
OE
5
6
6
D
7
4
D
5
D
4
2
D
3
D
8
9
GND
10
7
D
8
D
NOTES:
1. H = HIGH Voltage Level
X = Dont Care
L = LOW Voltage Level
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
Inputs
Outputs
xD
LE
OE
xQ
H
L
X
H
H
L
L
L
L
H
L
Q
(2)
X
X
H
Z
FUNCTION TABLE
(EACH LATCH)
(1)
Pin Names
OE
LE
xD
xQ
Description
Output Enable Inputs (Active LOW)
Latch Enable Input
Data Inputs
3-State Data Outputs
PIN DESCRIPTION
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