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參數(shù)資料
| 型號： | IDT74LVC573ASO |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O |
| 中文描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 1.27 MM PITCH, SOIC-20 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 71K |
| 代理商： | IDT74LVC573ASO |
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC573A
3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH
1
MARCH 1999
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4627/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μ
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SOIC, SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIV E FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVC573A
DESCRIPTION:
The LVC573A octal transparent D-type latch is built using advanced dual
metal CMOS technology. The device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads,
and is particularly suitable for implementing buffer registers, input-output (I/
O) ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data
(D) inputs. When LE is taken low, the Q outputs are latched at the logic levels
at the D inputs.
A buffered output-enable (
OE
) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without interface or pullup
components.
OE
does not affect the internal operations of the latch. Old data
can be retained or new data can be entered while the outputs are in the
high-impedance state.
The LVC573A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Inputs can be driven fromeither 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mxed 3.3V/5V systemenviron-
ment.
3.3V CMOS OCTAL
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
OE
C
1
1
D
LE
1
D
TO SEVEN OTHER CHANNELS
1
11
2
19
1
Q
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74LVC827APY | 制造商:Integrated Device Technology Inc 功能描述: |
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