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參數(shù)資料
| 型號： | IDT74LVC823A |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O |
| 中文描述： | 3.3V的CMOS 9位總線接口觸發(fā)器具有三態(tài)輸出和5伏電壓的I / O |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IDT74LVC823A |
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC823A
3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
1
J ANUARY 2004
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-4608/2
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μ
W typ. static)
Rail-to-rail output swing for increased noise margin
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SSOP, QSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIV E FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVC823A
DESCRIPTION:
The LVC823A 9-bit bus-interface flip-flop is built using advanced dual
metal CMOS technology. The LVC823A device is designed specifically for
driving highly capacitive or relatively low-impedance loads. The device is
particularly suitable for implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working registers.
With the clock-enable (
CLKEN
) input low, the nine D-type edge-triggered
flip-flops enter data on the low-to-high transitions of the clock. Taking
CLKEN
high disables the clock buffer, latching the outputs. This device has
noninverting data (D) inputs. Taking the clear (
CLR
) input low causes the
nine Q outputs to go low, independently of the clock.
A buffered output-enable (
OE
) input can be used to place the nine outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state.
OE
does not affect internal operations of the latch. Previously stored
data can be retained or new data can be entered while the outputs are in
the high-impedance state.
The LVC823A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
To ensure the high-impedance state during power up or power down,
OE
should be tied to V
CC
through a pullup resistor; the mnimumvalue of
the resistor is determned by the current-sinking capability of the driver.
Inputs can be driven fromeither 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mxed 3.3V/5V systemenvironment.
3.3V CMOS 9-BIT
BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
OE
C
1
1
D
CLKEN
1
D
TO EIGHT OTHER CHANNELS
1
14
2
23
1
Q
CLR
11
13
CLK
R
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
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|---|---|
| IDT74LVC823APG | 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74LVC827APY | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT74LVC861AEPG | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT74LVCC3245APGG | 功能描述:IC BUS TRANSCVR 3-ST 8B 24TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:74LVCC 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:100 系列:- 邏輯功能:變換器，雙向 位數(shù):2 輸入類型:CMOS 輸出類型:CMOS 數(shù)據(jù)速率:16Mbps 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應商設備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
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