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參數(shù)資料
| 型號： | IDT74FCT88915TT70PY8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDT74FCT88915TT70PY8 |
2
COMMERCIALTEMPERATURERANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
R
S
T
V
C
Q
5
G
N
D
Q
4
V
C
2
Q
Q/2
GND
Q3
VCC
Q2
GND
LOCK
P
L
_
E
N
G
N
D
Q
1
V
C
Q
0
G
N
D
F
R
E
Q
_
S
E
L
FEEDBK
REF_SEL
SYNC(0)
VCC(AN)
LF
GND(AN)
SYNC(1)
28
43
21
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5
6
7
8
9
10
VCC
RST
FEEDBACK
1
2
3
4
20
19
18
17
16
15
14
13
Q4
12
11
GND
Q/2
REF_SEL
SYNC(0)
VCC(AN)
LF
VCC
GND
Q3
VCC
Q2
GND
GND(AN)
LOCK
Q5
2Q
21
22
23
24
SYNC(1)
FREQ_SEL
GND
Q0
VCC
Q1
GND
PLL_EN
25
26
27
28
SSOP
TOP VIEW
PLCC
TOP VIEW
PIN CONFIGURATIONS
Pin Name
I/O
Description
SYNC(0)
I
Referenceclockinput
SYNC(1)
I
Referenceclockinput
REF_SEL
I
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
FREQ_SEL
I
Selects between ÷ 1 and ÷ 2 frequency options (refer to functional block diagram)
FEEDBACK
I
Feedbackinputtophasedetector
LF
I
Input for external loop filter connection
Q0-Q4
O
Clock outputs
Q5
O
Inverted clock output
2Q
O
Clock output (2 x Q frequency)
Q/2
O
Clock output (Q frequency ÷ 2)
LOCK
O
Indicates phase lock has been achieved (HIGH when locked)
RST
I
Asynchronous reset (active LOW)
PLL_EN
I
Disables phase-lock for low frequency testing (refer to functional block diagram)
PIN DESCRIPTION
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