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參數(shù)資料
| 型號： | IDT74FCT88915TT70PY8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDT74FCT88915TT70PY8 |
10
COMMERCIALTEMPERATURERANGE
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
Propagation Delay, Output Skew
Test Circuits For All Outputs
Pulse
G enerator
R T
D.U.T.
V CC
V IN
VOUT
500
Ω
50pF
C L
tPD
SYNC IN PUT
(SYNC (1) or
SYNC (0))
FEED BACK
INPUT
Q/2 OUTPUT
Q0-Q4
OUTPUTS
Q5 OUTPUT
2Q O UTPUT
tSKEW ALL
1.5V
tCYCLE SYNC INPUT
tSKEW f
tSKEW r
tSKEWf
tCYCLE "Q" OUTPUTS
tSKEW r
NOTES:
1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input. Therefore, the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point.
3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice
the SYNC frequency, and the Q/2 output would run at half the SYNC frequency.
(These waveforms represent the configuration shown in Figure 4a)
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