參數(shù)資料
型號: IDT74ALVCHR162269APF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: ALVC/VCX/A SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56
封裝: 0.40 MM PITCH, TVSOP-56
文件頁數(shù): 1/7頁
文件大?。?/td> 80K
代理商: IDT74ALVCHR162269APF
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH162269A
3.3VCMOS12-BITTO24-BITREGISTEREDBUSEXCHANGER
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4239/1
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
Balanced Output Drivers: ±12mA
Low Switching Noise
IDT74ALVCHR162269A
3.3V CMOS 12-BIT TO
24-BIT REGISTERED BUS
EXCHANGER WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This 12-bit to 24-bit registered bus exchanger is used in applications in
which two separate ports must be multiplexed onto, or demultiplexed from,
asingleport.Itisparticularlysuitableasaninterfacebetweensynchronous
DRAMs and high-speed microprocessors.
DataisstoredintheinternalB-portregistersonthelow-to-hightransition
of the clock (CLK) input when the appropriate clock-enable (CLKENA)
inputs are low. Proper control of these inputs allows two sequential 12-bit
words to be presented as a 24-bit word on the B-port. For data transfer
intheB-to-Adirection,asinglestorageregisterisprovided.Theselect SEL
line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, thus extending the period during
which the data is valid on the bus. The control terminals are registered so
that all transactions are synchronous with CLK. Data flow is controlled by
the active-low output enables (OEA, OEB1 and OEB2).
The ALVCHR162269A has series resistors in the device output struc-
ture which will significantly reduce line noise when used with light loads.
This driver has been designed to drive ±12mA at the designated threshold
levels.
TheALVCHR162269Ahas“bus-hold”whichretainstheinputs’laststate
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
OEB2
OEB1
CLK
CLKENA1
OEA
1
B1
SEL
0
1
CLKENA2
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
CE
1D
C1
CE
1D
C1
A1
2
B1
1 of 12 Channels
29
2
56
30
55
28
1
23
6
8
相關(guān)PDF資料
PDF描述
IDT74ALVCHR162269APAG ALVC/VCX/A SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56
IDT74ALVCHR162601PF ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
IDT74ALVCHR16500PV ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
IDT74ALVCHR16501PA8 ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
IDT74ALVCHR16543PF ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
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