參數(shù)資料
型號: IDT74ALVCHR162601PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: 0.40 MM PITCH, TVSOP-56
文件頁數(shù): 1/7頁
文件大?。?/td> 132K
代理商: IDT74ALVCHR162601PF
1
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74ALVCHR162601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
MARCH 1999
1999
Integrated Device Technology, Inc.
DSC-4491/1
c
IDT74ALVCHR162601
EXTENDED COMMERCIAL TEMPERATURE RANGE
Functional Block Diagram
3.3V CMOS 18-BIT
UNIVERSAL BUS
TRANSCEIVER WITH 3-STATE
OUTPUTS AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(0) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
Extended commercial range of – 40°C to + 85°C
–VCC = 3.3V ± 0.3V, Normal Range
–VCC = 2.7V to 3.6V, Extended Range
–VCC = 2.5V ± 0.2V
CMOS power levels (0.4 W typ. static)
Rail-to-Rail output swing for increased noise margin
APPLICATIONS:
3.3V High Speed Systems
3.3V and lower voltage computing systems
B 1
A 1
LE AB
CLKB A
OE BA
LE BA
CLKA B
TO 17 OTHE R CHANNE LS
CE
1D
C1
CE
1D
C1
CLK
CLKE NAB
OE AB
CLKE NBA
27
29
30
2
28
55
56
1
3
54
CLK
Drive Features for ALVCHR162601:
Balanced Output Drivers: ±12mA
Low switching noise
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The transceiver combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (
OEAB and
OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (
CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the data
is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output
enable
OEABisactivelow.When OEABislow,theoutputsareactive.When
OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA,LEBA,CLKBA
and
CLKENBA.
The ALVCHR162601 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCHR162601 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
相關PDF資料
PDF描述
IDT74ALVCHR16500PV ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
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