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參數(shù)資料
| 型號： | IDT74ALVCH162525PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.40 MM PITCH, TVSOP-56 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 132K |
| 代理商： | IDT74ALVCH162525PF8 |
1
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER
MARCH 1999
1999 Integrated Device Technology, Inc.
DSC-4220/-
c
IDT74ALVCH162525
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT REGIS-
TERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
output-enable (OEAB and OEBA) and clock-enable (CLKENAB and
CLKENBA) inputs. For the A-to-B data flow, the data flows through a
FEATURES:
–
0.5 MICRON CMOS Technology
–Typical tSK(0) (Output Skew) < 250ps
–
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
–
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
–
Extended commercial range of – 40°C to + 85°C
–VCC = 3.3V ± 0.3V, Normal Range
–VCC = 2.7V to 3.6V, Extended Range
–VCC = 2.5V ± 0.2V
–
CMOS power levels (0.4 W typ. static)
–
Rail-to-Rail output swing for increased noise margin
APPLICATIONS:
3.3V High Speed Systems
3.3V and lower voltage computing systems
Drive Features for ALVCH162525:
–
High Output Drivers: ±24mA (A port)
–
Balanced Output Drivers: ±12mA (B port)
single register. The B-to-A data can flow through a four-stage pipeline
register path, or through a single register path, depending on the state
of the select (SEL) input. Data is stored in the internal registers on the low-
to-high transition of the clock (CLK) input, provided that the appropriate
CLKEN inputs are low. The A-to-B data transfer is synchronized to the
CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA
and CLK2BA inputs.
The ALVCH162525 has series resistors in the device output structure
of the “B” port which will significantly reduce line noise when used with light
loads. This driver has been designed to drive ±12mA at the designated
threshold levels. The “A” port has a ±24mA driver.
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor; the minimum value
of the resistor is determined by the current-sinking capability of the
driver.
The ALVCH162525 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
Functional Block Diagram
B1
CE
C1
1D
1
0
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
OEB A
54
A1
SEL
OEA B
CLKE NAB
CLKE NBA
CLK 2 B A
CLK 1B A
CL
KA B
55
30
29
28
1
2
27
56
1 of 18 Channels
3
To 17 O th er Channe ls
DESCRIPTION:
This 18-bit registered bus transceiver is built using advanced dual
metal CMOS technology. Data flow in each direction is controlled by
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| IDT74ALVCH162825APF | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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