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參數(shù)資料
| 型號： | IDT74ALVCH16269PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, DUAL 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.40 MM PITCH, TVSOP-56 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 78K |
| 代理商： | IDT74ALVCH16269PF8 |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16269
3.3VCMOS12-BITTO24-BITREGISTEREDBUSEXCHANGER
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4588/2
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA (A port)
Suitable for heavy loads
OEB2
OEB1
CLK
CLKENA1
OEA
1
B1
SEL
0
1
CLKENA2
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
CE
1D
C1
CE
1D
C1
A1
2
B1
1 of 12 Channels
29
2
56
30
55
28
1
23
6
8
IDT74ALVCH16269
3.3V CMOS 12-BIT TO
24-BIT REGISTERED BUS
EXCHANGER WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This12-bitto24-bitregisteredbusexchangerisusedinapplicationsinwhich
twoseparateportsmustbemultiplexedonto,ordemultiplexedfrom,asingleport.
ItisparticularlysuitableasaninterfacebetweensynchronousDRAMsandhigh-
speedmicroprocessors.
DataisstoredintheinternalB-portregistersonthelow-to-hightransitionof
theclock(CLK)inputwhentheappropriateclock-enable(CLKENA)inputsare
low. Proper control of these inputs allows two sequential 12-bit words to be
presentedasa24-bitwordontheB-port.FordatatransferintheB-to-Adirection,
asinglestorageregisterisprovided.TheselectSELlineselects1Bor2Bdata
fortheAoutputs.TheregisterontheAoutputpermitsthefastestpossibledata
transfer,thusextendingtheperiodduringwhichthedataisvalidonthebus.The
control terminals are registered so that all transactions are synchronous with
CLK.Dataflowiscontrolledbytheactive-lowoutputenables(OEA,OEB1and
OEB2).
The ALVCH16269 has been designed with a ±24mA output driver. This
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
TheALVCH16269has“bus-hold”whichretainstheinputs’laststatewhen-
ever the input goes to a high impedance. This prevents floating inputs and
eliminatestheneedforpull-up/downresistors.
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