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參數(shù)資料
| 型號： | IDT72V70200PFG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 18/23頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 512X512 3.3V 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 72V |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 16:16 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V70200PFG8 |
4
COMMERCIALTEMPERATURERANGE
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
.UNCTIONAL DESCRIPTION
The IDT72V70200 is capable of switching 512 x 512, 64 Kbit/s PCM or
N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.
The serial input streams of the IDT72V70200 can have a bit rate of
2.048Mb/sandarearrangedin125
swideframes,whichcontain32channels
respectively. The data rates on input and output streams are identical.
In Processor Mode, the microprocessor can access input and output time-
slotsonaperchannelbasisallowingfortransferofcontrolandstatusinformation.
The IDT72V70200 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS or GCI
formats.
With the variety of different microprocessor interfaces, IDT72V70200 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfacesprovidecompatibilitywithmultiplexedandMotorolanon-multiplexed
buses. Thedevicecanalsoresolvedifferentcontrolsignalseliminatingtheuse
of glue logic necessary to convert the signals (R/
W/WR, DS/RD, AS/ALE).
Theframeoffsetcalibrationfunctionallowsuserstomeasuretheframeoffset
delay using a frame evaluation pin (FE). The input offset delay can be
programmedforindividualstreamsusinginternalframeinputoffsetregisters,see
Table 8.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT72V70200 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8KHz
input frame pulse (
F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 512 bytes.
Data to be output on the serial streams (TX0-15) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
tobeoutputfromconnectionmemory,theconnectionmemorycontrolbitsmust
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
IntheConnectionMode,theaddressesoftheinputsourcedataforalloutput
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
theoutputstreams.Fordetailsontheuseofthesourceaddressdata(CABand
SAB bits), see Table 10. Once the source address bits are programmed by the
microprocessor, the contents of the data memory at the selected address are
transferredtotheparallel-to-serialconvertersandthenontoaTXoutputstream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
outputstreamandchannelnumberandistransferreddirectlytotheparallel-to-
serial converter one time-slot before it is to be output. This data will be output
ontheTXstreamsineveryframeuntilthedataischangedbythemicroprocessor.
AstheIDT72V70200canbeusedinawidevarietyofapplications,thedevice
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V70200 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function.Inaddition,oneofthesebitsallowstheusertocontroltheCCOoutput.
Ifanoutputchannelissettoahigh-impedancestatethroughtheconnection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS
outputscanbeplacedinahighimpedancestatebyeitherpullingtheODEinput
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connectionmemorybits.
The connection memory data can be accessed via the microprocessor
interface.Theaddressingofthedevicesinternalregisters,dataandconnection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 3 and 5).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The
input and output stream data rates will always be identical.
The input 8 KHz frame pulse can be in either ST-BUS or GCI format. The
IDT72V70200 automatically detects the presence of an input frame pulse and
identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling
edge of the master clock marks a bit boundary and the data is clocked in on the
rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In
GCIformat,everysecondrisingedgeofthemasterclockmarksthebitboundary
and data is clocked in on the falling edge of CLK at three quarters of the way
into the bit cell, see Figure 8.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.
F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
dataisoftendelayed,thisfeatureisusefulincompensatingfortheskewbetween
clocks.
Each input stream can have its own delay offset value by programming the
frameinputoffsetregisters(FOR).Themaximumallowableskewis+4.5master
clock(CLK)periodsforwardwithresolutionofclockperiod.Theoutputframe
offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70200 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
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