參數(shù)資料
型號(hào)： IDT72V51436L7-5BB
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 57/57頁(yè)
文件大小： 0K
描述： IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝： 1
類型： 多隊(duì)列流量控制
安裝類型： 表面貼裝
封裝/外殼： 256-BBGA
供應(yīng)商設(shè)備封裝： 256-BGA（17x17）
包裝： 托盤
其它名稱： 72V51436L7-5BB
9
IDT72V51436/72V51446/72V51456 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OV
Output Valid Flag
LVTTL
the
OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-
(Continued)
OUTPUT
Impedance capability, required when multiple devices are used and the
OV flags are tied together.
OW(1)
OutputWidth
LVTTL
This pin is setup during Master Reset and must not toggle during any device operation. This pin is used
INPUT
in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9,
x18 or x36, (providing that one port is x36).
PAE
Programmable
LVTTL
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
Almost-EmptyFlag
OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queue is almost-empty. This flag output may be duplicated on one of the
PAEn bus lines. This flag is
synchronized to RCLK.
PAEn/PRn
Programmable
LVTTL
On the 16Q device the
PAEn/ PRn bus is 8 bits wide. During a Master Reset this bus is setup for either
Almost-EmptyFlag
OUTPUT
Almost Empty mode or Packet mode. This output bus provides
PAE/ PRnstatusof8queues(1sector),
Bus/Packet Ready
within a selected device, having a total of 2 sectors. During queue read/write operations these outputs
Flag Bus
provideprogrammableemptyflagstatusorpacketreadystatus,ineitherdirectorpolledmode.Themode
of flag operation is determined during master reset via the state of the FM input. This flag bus is capable
ofHigh-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirectoperation
the
PAEn/PRnbusisupdatedtoshowthePAE/PRstatusofasectorofqueueswithinaselecteddevice.
SelectionismadeusingRCLK,ESTRandRDADD.DuringPolledoperationthe
PAEn/PRnbusisloaded
with the
PAE/ PRn status of multi-queue flow-control sectors sequentially based on the rising edge of
RCLK.
PAE or PR operation is determined by the state of PKT during master reset.
PAF
Programmable
LVTTL
This pin provides the Almost-Full flag status for the queue that has been selected on the input port for
Almost-FullFlag
OUTPUT
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue
is almost-full. This flag output may be duplicated on one of the
PAFnbuslines.Thisflagissynchronized
toWCLK.
PAFn
Programmable
LVTTL
On the 16Q device the
PAFn bus is 8 bits wide. At any one time this output bus provides PAF status of
Almost-Full Flag Bus
OUTPUT
8 queues (1 sector), within a selected device, having a total of 2 sectors. During queue read/write
operations these outputs provide programmable full flag status, in either direct or polled mode. The mode
of flag operation is determined during master reset via the state of the FM input. This flag bus is capable
ofHigh-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirectoperation
the
PAFnbusisupdatedtoshowthePAFstatusofasectorofqueueswithinaselecteddevice.Selection
ismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolledoperationthe
PAFnbusisloadedwith
the
PAF statusofmulti-queueflow-controlsectorssequentiallybasedontherisingedgeofWCLK.
PKT(1)
Packet Mode
LVTTL
The state of this pin during a Master Reset will determine whether the part is operating in Packet mode
INPUT
providing both a Packet Ready (
PR) output and a Programmable Almost Empty (PAE) discrete output,
or standard mode, providing a (
PAE) output only. If this pin is HIGH during Master Reset the part will
operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read
port flag bus becomes packet ready flag bus,
PRn and the discrete packet ready flag, PR is functional.
If almost empty operation has been selected then the flag bus provides almost empty status,
PAEnand
thediscretealmostemptyflag,
PAEisfunctional,thePRflagisinactiveandshouldnotbeconnected.Packet
Readyutilizesusermarkedlocationstoidentifystartandendofpacketsbeingwrittenintothedevice. Packet
Mode can only be selected if both the input port width and output port width are 36 bits.
PR
Packet Ready Flag
LVTTL
If packet mode has been selected this flag output provides Packet Ready status of the queue selected
OUTPUT
for read operations. During a master reset the state of the PKT input determines whether Packet mode
of operation will be used. If Packet mode is selected, then the condition of the
PR flag andOV signalare
asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end of
a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet (EOP)
markers,themulti-queuedevicesets
PRLOWifoneormore“complete”packetsareavailableinthequeue.
A complete packet(s) must be written before the user is allowed to switch queues.
PRS
PartialReset
LVTTL
APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
INPUT
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking
PRS LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O TYPE
Description
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IDT72V51436L7-5BB8 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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IDT72V51443L6BB 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51443L6BB8 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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