參數(shù)資料
型號： IDT72V51436L7-5BB
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 18/57頁
文件大?。?/td> 0K
描述： IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝： 1
類型： 多隊列流量控制
安裝類型： 表面貼裝
封裝/外殼： 256-BBGA
供應(yīng)商設(shè)備封裝： 256-BGA（17x17）
包裝： 托盤
其它名稱： 72V51436L7-5BB
25
IDT72V51436/72V51446/72V51456 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
Output Valid,
OV Flag Boundary
I/O Set-Up
OV Boundary Condition
In36 to out36 (Almost Empty Mode)
OV Goes LOW after 1st Write
(Both ports selected for same queue
(see note 1 below for timing)
when the 1st Word is written in)
In36 to out36 (Packet Mode)
OV Goes LOW after 1st Write
(Both ports selected for same queue
(see note 2 below for timing)
when the 1st Word is written in)
In36 to out18
OV Goes LOW after 1st Write
(Both ports selected for same queue
(see note 1 below for timing)
when the 1st Word is written in)
In36 to out9
OV Goes LOW after 1st Write
(Both ports selected for same queue
(see note 1 below for timing)
when the 1st Word is written in)
In18 to out36
OV Goes LOW after 1st Write
(Both ports selected for same queue
(see note 1 below for timing)
when the 1st Word is written in)
In9 to out36
OV Goes LOW after 1st Write
(Both ports selected for same queue
(see note 1 below for timing)
when the 1st Word is written in)
NOTE:
1.
OV Timing
Assertion:
Write to
OV LOW: tSKEW1 + RCLK + tROV
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV
De-assertion:
Read Operation to
OV HIGH: tROV
2.
OV Timing when in Packet Mode (36 in to 36 out only)
Assertion:
Write to
OV LOW: tSKEW4 + RCLK + tROV
If tSKEW4 is violated there may be 1 added clock: tSKEW4 + 2 RCLK + tROV
De-assertion:
Read Operation to
OV HIGH: tROV
NOTE:
D = Queue Depth
FF Timing
Assertion:
Write Operation to
FF LOW: tWFF
De-assertion:
Read to
FF HIGH: tSKEW1 + tWFF
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
Full Flag,
FF Boundary
I/O Set-Up
FF Boundary Condition
In36 to out36
FF Goes LOW after D+1 Writes
(Both ports selected for same queue
(see note below for timing)
when the 1st Word is written in)
In36 to out36
FF Goes LOW after D Writes
(Write port only selected for queue
(see note below for timing)
when the 1st Word is written in)
In36 to out18
FF Goes LOW after D Writes
(Both ports selected for same queue
(see note below for timing)
when the 1st Word is written in)
In36 to out18
FF Goes LOW after D Writes
(Write port only selected for queue
(see note below for timing)
when the 1st Word is written in)
In36 to out9
FF Goes LOW after D Writes
(Both ports selected for same queue
(see note below for timing)
when the 1st Word is written in)
In36 to out9
FF Goes LOW after D Writes
(Write port only selected for queue
(see note below for timing)
when the 1st Word is written in)
In18 to out36
FF Goes LOW after ([D+1] x 2) Writes
(Both ports selected for same queue
(see note below for timing)
when the 1st Word is written in)
In18 to out36
FF Goes LOW after (D x 2) Writes
(Write port only selected for queue
(see note below for timing)
when the 1st Word is written in)
In9 to out36
FF Goes LOW after ([D+1] x 4) Writes
(Both ports selected for same queue
(see note below for timing)
when the 1st Word is written in)
In9 to out36
FF Goes LOW after (D x 4) Writes
(Write port only selected for queue
(see note below for timing)
when the 1st Word is written in)
Programmable Almost Full Flag,
PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
in36 to out36
PAF/PAFn Goes LOW after
(Both ports selected for same queue when the 1st
D+1-m Writes
Word is written in until the boundary is reached)
(see note below for timing)
in36 to out36
PAF/PAFn Goes LOW after
(Write port only selected for same queue when the D-m Writes
1st Word is written in until the boundary is reached) (see note below for timing)
in36 to out18
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
in36 to out9
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
in18 to out36
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(see note below for timing)
in9 to out36
PAF/PAFn Goes LOW after
([D+1-m] x 4) Writes
(seenotebelowfortiming)
NOTE:
D = Queue Depth
m = Almost Full Offset value.
Default values:
if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
Assertion:
Write Operation to
PAF LOW: 2 WCLK + tWAF
De-assertion: Read to
PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
Assertion:
Write Operation to
PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to
PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
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