參數(shù)資料
型號(hào): IDT72V51256L7-5BB
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 22/56頁(yè)
文件大?。?/td> 0K
描述: IC FLOW CTRL MULTI QUEUE 256-BGA
標(biāo)準(zhǔn)包裝: 1
類型: 多隊(duì)列流量控制
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-BGA(17x17)
包裝: 托盤
其它名稱: 72V51256L7-5BB
29
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
FF
tRSF
OV
tRSF
PAF
tRSF
PAE
tRSF
PR
tRSF
Qn
tRSF
LOGIC "1" if
OE is LOW and device is Master
HIGH-Z if
OE is HIGH or Device is Slave
HIGH-Z if Slave Device
LOGIC “0" if Master Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PAFn
PAEn
PRn
tRS
MRS
WEN
REN
tRSS
FSTR,
ESTR
5937 drw09
tRSR
SENI
WADEN,
RADEN
tRSS
OW, IW,
BM
DF
FM
HIGH = Looped
LOW = Strobed (Direct)
ID0, ID1,
ID2
tRSS
HIGH = Packet Ready Mode
LOW = Almost Empty
MAST
PKT
DFM
HIGH = Master Device
LOW = Slave Device
HIGH = Default Programming
LOW = Serial Programming
HIGH = Offset Value is 128
LOW = Offset value is 8
tRSS
Figure 4. Master Reset
NOTES:
1.
OE can toggle during this period.
2.
PRS should be HIGH during a MRS.
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