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| 型號： | IDT72V51256L7-5BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 標準包裝： | 1 |
| 類型： | 多隊列流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應商設備封裝： | 256-BGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 72V51256L7-5BB |
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NULL QUEUE OPERATION (OF THE READ PORT)
Pipelining of data to the output port enables the device to provide 100% bus
utilizationinstandardmode.Datacanbereadoutofthemulti-queueflow-control
device on every RCLK cycle regardless of queue switches or other opera-
tions. The device architecture is such that the pipeline is constantly filled with
the next words in a selected queue to be read out, again providing 100% bus
utilization. This type of architecture does assume that the user is constantly
switching queues such that during a queue switch, the last data word required
from the previous queue will fall through the pipeline to the output.
Note,thatifreadsceaseattheemptyboundaryofaqueue,thenthelastword
will automatically flow through the pipeline to the output.
The Null-Q is selected via read port address space RDADD[2]. The
RDADD[5:0] bus should be addressed with xxx1xx, this address is the Null-Q.
A null queue can be selected when no further reads are required from a
previouslyselectedqueue.Changingtoanullqueuewillcontinuetopropagate
data in the pipeline to the previous queue’s output. The Null Q can remain
selecteduntiladatabecomesavailableinanotherqueueforreading.TheNull-
Q can be utilized in either standard or packet mode.
Note: If the user switches the read port to the null queue, this queue is seen
as and treated as an empty queue, therefore after switching to the null queue
the last word from the previous queue will remain in the output register and the
OV flag will go HIGH, indicating data is not valid.
The Null queue operation only has significance to the read port of the multi-
queue, it is a means to force data through the pipeline to the output. Null Q
selection and operation has no meaning on the write port of the device. Also,
refer to Figure 20, Read Operation and Null Queue Select for diagram.
PAFn FLAG BUS OPERATION
The IDT72V51236/72V51246/72V51256 multi-queue flow-control devices
can be configured for up to 4 queues, each queue having its own almost full
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,
FFandPAF,
on the write port. Queues that are not selected for a write operation can have
their
PAFstatusmonitoredviathePAFnbus.ThePAFnflagbusis4bitswide,
so that all 4 queues can have their status output to the bus. When a single
multi-queue device is used anywhere from 1 to 4 queues may be set-up within
thepart,eachqueuehavingitsowndedicated
PAFflagoutputonthePAFnbus.
Queues 1 through 4 have their
PAF status to PAF[0] through PAF[3]
respectively. If less than 4 queues are used then only the associated
PAFn
outputswillberequired,unused
PAFnoutputswillbedon’tcareoutputs.When
devices are connected in expansion mode the
PAFn flag bus can also be
expanded beyond 4 bits to produce a wider
PAFn bus that encompasses all
queues.
Alternatively,the4bit
PAFnflagbusofeachdevicecanbeconnectedtogether
to form a single 4 bit bus, i.e.
PAF[0]ofdevice1willconnecttoPAF[0]ofdevice
2 etc. When connecting devices in this manner the
PAFn can only be driven
by a single device at any time, (the
PAFn outputs of all other devices must be
in high impedance state). There are two methods by which the user can select
which device has control of the bus, these are “Direct” (Addressed) mode or
“Polled” (Looped) mode, determined by the state of the FM (flag Mode) input
during a Master Reset.
EXPANDING UP TO 32 QUEUES OR PROVIDING DEEPER QUEUES
Expansion can take place using either the standard mode or the packet
mode. In the 4 queue multi-queue device, the WRADD address bus is 5 bits
wide. The 2 Least Significant bits (LSbs) are used to address one of the 4
availablequeueswithinasinglemulti-queuedevice.The3MostSignificantbits
(MSbs) are used when a device is connected in expansion mode with up to
8 devices connected in width expansion, each device having its own 3-bit
address. When logically expanded with multiple parts, each device is statically
setup with a unique chip ID code on the ID pins, ID0, ID1, and ID2. A device
isselectedwhenthe3MostSignificantbitsoftheWRADDaddressbusmatches
a 3-bit ID code. The maximum logical expansion is 32 queues (4 queues x
8 devices) or a minimum of 8 queues (1 queue per device x 8 devices), each
of the maximum size of the individual memory device.
Note: The WRADD bus is also used in conjunction with FSTR (almost full
flag bus strobe), to address the almost full flag bus during direct mode of
operation.
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
11, Full Flag Timing Expansion Mode, Figure 13, Output Valid Flag Timing
(In Expansion Mode), and Figure 30, Multi-Queue Expansion Diagram, for
timingdiagrams.
BUS MATCHING OPERATION
Bus Matching operation between the input port and output port is available.
During a master reset of the multi-queue the state of the three setup pins, BM
(BusMatching),IW(InputWidth)andOW(OutputWidth)determinetheinputand
output port bus widths as per the selections shown in Table 3, “Bus Matching
Set-up”. 9 bit bytes, 18 bit words and 36 bit long words can be written into and
read from the queues provided that at least one of the ports is setup for x36
operation. When writing to or reading from the multi-queue in a bus matching
mode, the device orders data in a “Little Endian” format. See Figure 3, Bus
Matching Byte Arrangement for details.
The Full flag and Almost Full flag operation is always based on writes and
readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput
port is x36 and the output port is x9, then four data reads from a full queue will
be required to cause the full flag to go HIGH (queue not full). Conversely, the
OutputValidflagandAlmostEmptyflagoperationsarealwaysbasedonwrites
and reads of data widths determined by the read port. For example, if the input
port is x18 and the output port is x36, two write operations will be required to
cause the output valid flag of an empty queue to go LOW, output valid (queue
is not empty).
Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput
port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput
port size) and the output bus width from all queues is equal (determined by the
output port size).
BM
I W
OW
Write Port
Read Port
0
X
x36
1
0
x36
x18
1
0
1
x36
x9
1
0
x18
x36
1
x9
x36
TABLE 3
BUS-MATCHING SET-UP
FULL FLAG OPERATION
The multi-queue flow-control device provides a single Full Flag output,
FF.
The
FFflagoutputprovidesafullstatusofthequeuecurrentlyselectedonthe
write port for write operations. Internally the multi-queue flow-control device
monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however
onlythequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothe
FF flag. This dedicated flag is often referred to as the “active queue full flag”.
When queue switches are being made on the write port, the
FF flag output
will switch to the new queue and provide the user with the new queue status,
onthecycleafteranewqueueselectionismade.Theuserthenhasafullstatus
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| IDT72V51256L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51256L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
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