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| 型號： | IDT72V51256L7-5BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/56頁 |
| 文件大小： | 0K |
| 描述： | IC FLOW CTRL MULTI QUEUE 256-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 多隊列流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 72V51256L7-5BB |
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IDT72V51236/72V51246/72V51256 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
(REOP). The minimum size for a packet is four words (SOP, two words of data
and EOP). The almost empty flag bus becomes the “Packet Ready”
PR flag
buswhenthedeviceisconfiguredforpacketmode.Validpacketsareindicated
when both
PR and OV are asserted.
WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE)
Itisrequiredthatafullpacketbewrittentoaqueuebeforemovingtoadifferent
queue. The device requires two cycles to change queues. Packet mode, has
2 restrictions: <1> An extra word (or filler word) is required to be written after
each packet on the cycle following the queue change to ensure the RSOP in
the old queue is not read out on a queue change because of the first word fall
through. <2> No SOP/EOP is allowed to read/written at cycle (“C” or “I”) the
nextcycleafteraqueuechange.Forclockfrequency(fs)of133MHzandbelow
see Application Note AN-398. In this mode, the write port may not obtain 100%
busutilization
Changing queues requires a minimum of two WCLK cycles on the write port
(see Figure 16, Writing in Packet Mode during a Queue Change). WADEN
goes high signaling a change of queue (clock cycle “B” or “H”). The address
on WRADD at the rising edge of WCLK determines the next queue. Data
presented on Din during that cycle (“B” or “H”) can continue to be written to
the active (old) queue (Q
A or QB respectively), provided WEN is LOW (active).
If
WEN is HIGH (inactive) for this clock cycle (H), data will not be written in to
the previous queue (Q
B). The cycle following a request for queue change (“C”
or “I”) will require a filler word to be written to the device. This can be done
by clocking the TEOP twice or by writing a filler word. In packet mode, the multi-
queue is designed under the 2 restrictions listed previously. Note, an
erroneous Packet Ready flag may occur if the EOP or SOP marker shows up
atthenextcycleafteraqueuechange.TopreventanerroneousPacketReady
flag from occurring a filler word should be written into the old queue at the last
clockcycleofwriting.ItisimportanttoknowthatnoSOPorEOPmaybewritten
into the device during this cycle (“C” or “I”). The write port discrete full flag will
updatetoshowthefullstatusofthenewlyselectedqueue(Q
B) at this last cycle’s
rising edge (“C” or “I”). Data values presented on the data input bus (Din),
can be written into the newly selected queue (Q
X) on the rising edge of WCLK
on the second cycle (“D” or “J”) following a request for change of queue,
provided
WENisLOW(active)andthenewqueueisnotfull.Ifaselectedqueue
isfull(
FFisLOW),thenwritestothatqueuewillbeprevented.Note,datacannot
be written into a full queue.
Refer to Figure 16, Writing in Packet Mode during a Queue Change and
Figure 18, Data Input (Transit) packet mode of Operation for timing diagrams.
READ QUEUE SELECTION AND READ OPERATION (PACKET MODE)
In Packet Mode it is required that a full packet is read from a queue before
movingtoadifferentqueue.Thedevicerequirestwocyclestochangequeues.
In Packet Mode, there are 2 restrictions <1> An extra word (or filler word)
should have been inserted into the data stream after each packet to insure the
RSOP in the old queue is not read out on a queue change because of the first
word fall through and this word should be discarded. <2> No EOP/SOP is
allowed to be read/written at cycle (“C” or “I”) the next cycle after a queue
change). For clock frequency of 133Mhz and below see Application Note AN-
398. In this mode, the read port may not obtain 100% bus utilization
Changing queues requires a minimum of two RCLK cycles on the read port
(see Figure 17, Reading in Packet Mode during a Queue Change). RADEN
goes high signaling a change of queue (clock cycle “B” or “I”). The address
on RDADD at the rising edge of RCLK determines the queue. As illustrated
in Figure 17 during cycle (“B”), data can be read from the active (old) queue
(Q
A)), provided both REN and OE are LOW (active) simultaneously with
changing queues. REOP for packet located in queue (Q
A) must be read before
a queue change request is made (“B”). If
REN isHIGH(inactive)forthisclock
cycle (“I”), data will not be read from the previous queue (Q
B). In applications
where the multi-queue flow-control device is connected to a shared bus, an
output enable,
OE control pin is also provided to allow High-Impedance
selectionofthedataoutputs(Qout).WithreferencetoFigure17whenchanging
queues, a packet marker (SOP or EOP) should not be read on cycle (“C” or
“I”). Reading a SOP or EOP should not occur during the cycles required for
aqueuechange.Itisalsorecommendedthataqueuechangeshouldnotoccur
oncethereadingofthepackethascommenced.TheEOPmarkerofthepacket
prior to a queue change should be read on or before the queue change. If the
EOP word is read before a queue change, REN can be pulled high to disable
further reads. When the queue change is initiated, the filler word written into
the current queue after the EOP word will fall through followed by and the first
word from the new queue.
Refer to Figure 17, Reading in Packet Mode during a Queue Change as
well as Figures 12, 14, and 15 for timing diagrams and Table 2, for Read
Address bus arrangement.
Note,thealmostemptyflagbusbecomesthe“PacketReady”flagbuswhen
the device is configured for packet mode.
PACKET READY FLAG
The multi-queue flow-control device provides the user with a Packet Ready
feature. During a Master Reset the logic “1” (HIGH) on the PKT input signal
(packet mode select), configures the device in packet mode. The
PRdiscrete
flag, provides a packet ready status of the active queue selected on the read
port. A packet ready status is individually maintained on all queues; however
only the queue selected on the read port has its packet ready status indicated
on the
PRoutputflag.Apacketisavailableontheoutputforreadingwhenboth
PRandOVareassertedLOW.Iflessthanafullpacketisavailable,thePRflag
will be HIGH (packet not ready). In packet mode, no words can be read from
a queue until a complete packet has been written into that queue, regardless
of
REN.
WhenpacketmodeisselectedtheProgrammableAlmostEmptybus,
PAEn,
becomes the Packet Ready bus,
PRn. When configured in Direct Bus (FM =
LOW during a master reset), the
PRn bus provides packet ready status in 8
queue increments. The
PRn bus supports either Polled or Direct modes of
operation. The
PRn mode of operation is configured through the Flag Mode
(FM) bit during a Master Reset.
When the multi-queue is configured for packet mode operation, the device
must also be configured for 36 bit write data bus and 36 bit read data bus. The
two most significant bits of the 36-bit data bus are used as “packet markers”.
On the write port these are bits D34 (Transmit Start of Packet,) D35 (Transmit
End of Packet) and on the read port Q34, Q35. All four bits are monitored by
the packet control logic as data is written into and read out from the queues.
Thepacketreadystatusforindividualqueuesisthendeterminedbythepacket
ready logic.
On the write port D34 is used to “mark” the first word being written into the
selectedqueueasthe“TransmitStartofPacket”,TSOP.Tofurtherclarify,when
the user requires a word being written to be marked as the start of a packet,
the TSOP input (D34) must be HIGH for the same WCLK rising edge as the
word that is written. The TSOP marker is stored in the queue along with the
data it was written in until the word is read out of the queue via the read port.
On the write port D35 is used to “mark” the last word of the packet currently
being written into the selected queue as the “Transmit End of Packet” TEOP.
When the user requires a word being written to be marked as the end of a
packet, the TEOP input must be HIGH for the same WCLK rising edge as the
word that is written in. The TEOP marker is stored in the queue along with the
data it was written in until the word is read out of the queue via the read port.
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| IDT72V51256L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51256L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51333L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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