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42
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
Figure 31. Standard JTAG Timing
SYSTEM INTERFACE PARAMETERS
Parameter
Symbol
Test
Conditions
Min.
Max. Units
JTAG Clock Input Period tTCK
-
100
-
ns
JTAG Clock HIGH
tTCKHIGH
-40
-
ns
JTAG Clock Low
tTCKLOW
-40
-
ns
JTAG Clock Rise Time
tTCKRise
--
5(1)
ns
JTAG Clock Fall Time
tTCKFall
--
5(1)
ns
JTAG Reset
tRST
-50
-
ns
JTAG Reset Recovery
tRSR
-50
-
ns
JTAG AC ELECTRICAL
CHARACTERISTICS
(VCC = 3.3V
± 5%; Tcase = 0°C to +85°C)
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
Parameter
Symbol
Test Conditions
Min.
Max.
Units
DataOutput
tDO = Max
-
20
ns
Data Output Hold
tDOH(1)
0-
ns
Data Input
tDS
trise=3ns
10
-
ns
tDH
tfall=3ns
10
-
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
tTCK
t4
t2
t3
t1
tDS
tDH
TDO
TDI/
TMS
TCK
TRST
t5
tDO
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t3 = tTCKFALL
t4 = tTCKRise
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
4667 drw36
t6