IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號(hào)： IDT72V3690L7-5PF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 10/46頁(yè)
文件大小： 0K
描述： IC FIFO SS 32768X36 7-5N 128TQFP
標(biāo)準(zhǔn)包裝： 36
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 1.1M（32K x 36）
數(shù)據(jù)速率： 133MHz
訪(fǎng)問(wèn)時(shí)間： 5ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤(pán)
其它名稱(chēng)： 72V3690L7-5PF
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
if
EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When
EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on
REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting
OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When
ORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
the first word appears on the outputs, no LOW on
RENisnecessary.Reading
all subsequent words requires a LOW on
REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
For either IDT Standard mode or FWFT mode, updating of the
PAE, HF
and
PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafter
RTissetup,
the
PAEflagwillbeupdated. HFisasynchronous,thustherisingedgeofRCLK
that
RTissetupwillupdateHF. PAFissynchronizedtoWCLK,thusthesecond
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that
RT
is setup will update
PAF. RT is synchronized to RCLK.
The Retransmit function has the option of two modes of operation, either
“normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
latency” retransmit operation. Zero latency basically means that the first data
word to be retransmitted, is placed onto the output register with respect to the
RCLK pulse that initiated the retransmit.
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參數(shù)描述
IDT72V3690L7-5PF8 功能描述:IC FIFO SS 32768X36 7-5N 128TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72V3690L7-5PFGI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 32768X36 7-5N 128TQFP
IDT72V3690L7-5PFGI8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 32768X36 7-5N 128TQFP
IDT72V3690L7-5PFI 功能描述:IC FIFO SS 32768X36 7-5N 128TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72V3692L10PF 功能描述:IC FIFO 131X18 10NS 120QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
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