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11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
4667 drw04
330
30pF*
510
3.3V
D.U.T.
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns(1)
Input Timing Reference Levels
1.5V
OutputReferenceLevels
1.5V
Output Load for tCLK = 10ns, 15 ns
See Figure 2a
Output Load for tCLK = 6ns, 7.5ns
See Figure 2b & 2c
AC TEST CONDITIONS
Figure 2b. AC Test Load
Figure 2c. Lumped Capacitive Load, Typical Derating
AC TEST LOADS - 6ns, 7.5ns Speed Grades
Figure 2a. Output Load
* Includes jig and scope capacitances.
ACTESTLOADS-10ns,15nsSpeedGrades
NOTE:
1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns.
4667 drw04a
50
1.5V
I/O
Z0 = 50
4667 drw04b
6
5
4
3
2
1
20 30 50
80 100
200
Capacitance (pF)
tCD
(Typical,
ns)
VIH
OE
VIL
tOE & tOLZ
VCC
2
VCC
2
100mV
tOHZ
100mV
Output
Normally
LOW
Output
Normally
HIGH
VOL
VOH
VCC
2
VCC
2
4667 drw04c
Output
Enable
Output
Disable
OUTPUT ENABLE & DISABLE TIMING
NOTE:
1.
REN is HIGH.