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| 型號： | IDT72V3654L15PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BI FIFO 4096X36 15NS 128QFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | 72V |
| 功能： | 異步 |
| 存儲容量： | 147K（4K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3654L15PF |
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11
COMMERCIALTEMPERATURERANGE
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1, MRS2)
Afterpowerup,aMasterReset operationmustbeperformedbyproviding
a LOW pulse to
MRS1 and MRS2 simultaneously. Afterwards, each of the
two FIFO memories of the IDT72V3654/72V3664/72V3674 undergoes a
complete reset by taking its associated Master Reset (
MRS1, MRS2) input
LOW for at least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-
to-HIGH transitions. The Master Reset inputs can switch asynchronously to
the clocks. A Master Reset initializes the associated write and read pointers to
the first location of the memory and forces the Full/Input Ready flag (
FFA/IRA,
FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW,
the Almost-Empty flag (
AEA, AEB) LOW and forces the Almost-Full flag
(
AFA, AFB) HIGH. A Master Reset also forces the associated Mailbox Flag
(
MBF1, MFB2) of the parallel mailbox register HIGH. After a Master Reset,
the FIFO's Full/Input Ready flag is set HIGH after two write clock cycles. Then
the FIFO is ready to be written to.
A LOW-to-HIGH transition on the FIFO1 Master Reset (
MRS1) input
latches the values of the Big-Endian (BE) input for determining the order by
which bytes are transferred through Port B. It also latches the values of the
FlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-FullandAlmost-
Emptyoffsetprogrammingmethod.
A LOW-to-HIGH transition on the FIFO2 Master Reset (
MRS2) clears
the Flag Offset Registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the
FIFO2 Master Reset (
MRS2) together with the FIFO1 Master Reset (MRS1)
input latches the value of the Big-Endian (BE) input for Port B and also latches
thevaluesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-
Full and Almost-Empty offset programming method. (For details see Table 1,
Flag Programming, and the Programming the Almost-Empty and Almost-Full
Flags section). The relevant FIFO Master Reset timing diagram can be found
in Figure 3.
PARTIAL RESET (
PRS1, PRS2)
Each of the two FIFO memories of these devices undergoes a limited reset
by taking its associated Partial Reset (
PRS1, PRS2) input LOW for at least
four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH
transitions. The Partial Reset inputs can switch asynchronously to the clocks.
A Partial Reset initializes the internal read and write pointers and forces the
Full/Input Ready flag (
FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready
flag (
EFA/ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB)
LOW, and the Almost-Full flag (
AFA, AFB) HIGH. A Partial Reset also forces
the Mailbox Flag (
MBF1, MBF2) of the parallel mailbox register HIGH. After
a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two write
clock cycles. Then the FIFO is ready to be written to.
Whatever flag offsets, programming method (parallel or serial), and timing
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be inconvenient. See
Figure 4 for the Partial Reset timing diagram.
RETRANSMIT (
RT1, RT2)
The FIFO1 memory of these devices undergoes a Retransmit by taking its
associated Retransmit (
RT1)inputLOWforatleastfourPortAClock(CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializes the read pointer of FIFO1 to the first memory location.
The FIFO2 memory undergoes a Retransmit by taking its associated
Retransmit(
RT2)inputLOWforatleastfourPortAClock(CLKA)andfourPort
CClock(CLKC)LOW-to-HIGHtransitions.TheRetransmitinitializestheread
pointer of FIFO2 to the first memory location.
The RTM pin must be HIGH during the time of Retranmit. Note that the
RT1inputismuxedwiththePRS1input,thestateoftheRTMpindetermining
whether this pin performs a Retransmit or Partial Reset. Also, the
RT2inputis
muxed with the
PRS2input,thestateoftheRTMpindeterminingwhetherthis
pin performs a Retransmit or Partial Reset.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
— ENDIAN SELECTION
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction
is active, permitting a choice of Big or Little-Endian byte arrangement for data
written to or read from Port B. This selection determines the order by which
bytes (or words) of data are transferred through this port. For the following
illustrations, assume that a byte (or word) bus size has been selected for Port
B. (Note that when Port B is configured for a long word size, the Big-Endian
function has no application and the BE input is a “don’t care”1.)
A HIGH on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaBig-Endianarrangement.Whendata
is moving in the direction from Port A to Port B, the most significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When
data is moving in the direction from Port B to Port A, the byte (word) written
to Port B first will be read from Port A as the most significant byte (word) of the
long word; the byte (word) written to Port B last will be read from Port A as
the least significant byte (word) of the long word.
A LOW on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata
is moving in the direction from Port A to Port B, the least significant byte (word)
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When
data is moving in the direction from Port B to Port A, the byte (word) written
to Port B first will be read from Port A as the least significant byte (word) of the
long word; the byte (word) written to Port B last will be read from Port A as
the most significant byte (word) of the long word. Refer to Figure 2 for an
illustrationoftheBEfunction.SeeFigure3(MasterReset)fortheEndianselect
timingdiagram.
— TIMING MODE SELECTION
After Master Reset, the FWFT select function is active, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (
MRS1, MRS2) input is
HIGH, a HIGH on the BE/
FWFT input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select IDT Standard
mode. This mode uses the Empty Flag function (
EFA, EFB) to indicate
whether or not there are any words present in the FIFO memory. It uses the
Full Flag function (
FFA, FFB) to indicate whether or not the FIFO memory
has any free space for writing. In IDT Standard mode, every word read from
the FIFO, including the first, must be requested using a formal read operation.
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
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| IDT72V3654L15PF8 | 功能描述:IC BI FIFO 4096X36 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3656L10PF | 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3656L10PF8 | 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3656L10PFI | 制造商:Integrated Device Technology Inc 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP |
| IDT72V3656L10PFI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SYNC FIFO 4096X36 10NS 128QFP |
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