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參數(shù)資料
| 型號： | IDT72V3633L10PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 512X36 10NS 128TQFP |
| 標準包裝： | 72 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 18.4K（512 x 36） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3633L10PF |
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11
COMMERCIAL TEMPERATURERANGE
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
TABLE 1 — FLAG PROGRAMMING
SPM
FS1/
SEN
FS0/SD
RS1
X AND Y REGlSTERS(1)
HH
H
↑
64
HH
L
↑
16
HL
H
↑
8
HL
L
↑
Parallel programming via Port A
LH
L
↑
Serial Programming via SD
LH
H
↑
reserved
LL
H
↑
reserved
LL
L
↑
reserved
NOTE:
1. X register holds the offset for
AE; Y register holds the offset for AF.
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timingdiagram.ThePortAdatainputsusedbytheoffsetregistersare(A7-A0),
(A8-A0), or (A9-A0) for the IDT72V3623, IDT72V3633 or IDT72V3643,
respectively. The highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for the registers
range from 1 to 252 for the IDT72V3623; 1 to 508 for the IDT72V3633; and
1 to 1,020 for the IDT72V3643. After all the offset registers are programmed
from Port A, the FIFO begins normal operation.
— SERIAL LOAD
ToprogramtheXandYregistersserially,initiateaResetwith
SPMLOW,
FS0/SDLOWandFS1/
SENHIGHduringtheLOW-to-HIGHtransitionofRS1.
After this reset is complete, the X and Y register values are loaded bit-wise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the
FS1/
SENinputisLOW.Thereare16-,18-or20-bitwritesneededtocomplete
the programming for the IDT72V3623, IDT72V3633 or the IDT72V3643,
respectively. ThetworegistersarewrittenintheorderY,X. Eachregistervalue
can be programmed from 1 to 252 (IDT72V3623), 1 to 508 (IDT72V3633) or
1 to 1,020 (IDT72V3643).
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/
Input Ready (
FF/IR)flagremainsLOWuntilallregisterbitsarewritten. FF/IR
is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
See Figure 6, Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) lines is controlled by Port A Chip
Select (
CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in
the High-impedance state when either
CSA or W/RA is HIGH. The A0-A35
lines are active outputs when both
CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW,and
FF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent
of any concurrent reads on Port B.
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception
thatthePortBWrite/Readselect(
W/RB)istheinverseofthePortAWrite/Read
select (W/
RA). ThestateofthePortBdata(B0-B35)linesiscontrolledbythe
Port B Chip Select (
CSB)andPortBWrite/Readselect(W/RB). TheB0-B35
linesareinthehigh-impedancestatewheneither
CSBisHIGHorW/RBisLOW.
The B0-B35 lines are active outputs when
CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when
CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is
LOW,and
EF/ORisHIGH(seeTable3). FIFOreadsonPortBareindependent
of any concurrent writes on Port A.
The setup and hold time constraints to the port clocks for the port Chip
SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations
andarenotrelatedtohigh-impedancecontrolofthedataoutputs. Ifaportenable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is
LOW,thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterby
the LOW-to-HIGH transition of the port clock that sets the Output Ready flag
HIGH. WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemory
array is clocked to the output register only when a read is selected using the
port’s Chip Select, Write/Read select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, regardless of whether
the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is
clocked to the output register only when a read is selected using the port’s Chip
Select, Write/Read select, Enable, and Mailbox select. Port A Write timing
diagram can be found in Figure 7. Relevant Port B Read timing diagrams
together with Bus-Matching and Endian select can be found in Figure 8, 9 and
10.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability
of metastable events when CLKA and CLKB operate asynchronously to one
another.
FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
synchronized to CLKB. Table 4 shows the relationship of each port flag to the
number of words stored in memory.
EMPTY/OUTPUT READY FLAGS (
EF/OR)
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(OR)
functionisselected. WhentheOutput-ReadyflagisHIGH,newdataispresent
in the FIFO output register. When the Output Ready flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
IntheIDTStandardmode,theEmptyFlag(
EF)functionisselected. When
the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to
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| IDT72V3633L10PF8 | 功能描述:IC FIFO SYNC 512X36 10NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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