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參數(shù)資料
| 型號(hào)： | IDT72V3611L15PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 19/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 64X36 15NS 120-TQFP |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 2.3K（64 x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時(shí)間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 72V3611L15PF |
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IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIALTEMPERATURERANGE
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Functions
H
X
Input
None
L
H
L
X
Input
None
LH
H
L
↑
Input
None
LH
H
↑
Input
Mail2Write
L
X
Output
None
LL
H
L
↑
Output
FIFO Read
L
H
X
Output
None
LL
H
↑
Output
Mail1 Read (set MBF1 HIGH)
CSA
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Functions
H
X
Input
None
L
H
L
X
Input
None
LH
H
L
↑
Input
FIFOWrite
LH
H
↑
Input
Mail1Write
L
X
Output
None
LL
H
L
↑
Output
None
L
H
X
Output
None
LL
H
↑
Output
Mail2 Read (set MBF2 HIGH)
Almost-Full and
Almost-Empty Flag
FS1
FS0
RST
Offset Register (X)
16
H
↑
12
H
L
↑
8L
H
↑
4L
L
↑
SIGNAL DESCRIPTION
RESET ( RST )
The IDT72V3611 is reset by taking the Reset (RST) input LOW for at
least four port-A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH
transitions. Theresetinputcanswitchasynchronouslytotheclocks. Adevice
resetinitializestheinternalreadandwritepointersoftheFIFOandforcesthe
FullFlag(FF)LOW,theEmptyFlag(EF)LOW,theAlmost-Emptyflag(AE)LOW,
and the Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags
(MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH
transitions of CLKA. The device must be reset after power up before data is
writtentoitsmemory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Empty Offset register (X) with the value selected by the Flag Select
(FS0, FS1) inputs. The values that can be loaded into the register are shown
in Table 1. For the relevant Reset timing and preset value loading timing
diagram,seeFigure2. TherelevantWritetimingdiagramforPortAcanbefound
in Figure 3.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled by the port-
A Chip Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35
outputs are in the high-impedance state when either CSA or W/RA is HIGH.
The A0-A35 outputs are active when both CSA and W/RA are LOW. Data
is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH transition
of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and
FF is HIGH (see Table 2).
The port-B control signals are identical to those of port A. The state of
the port-B data (B0-B35) outputs is controlled by the port-B Chip Select
(CSB) and the port-B Write/Read select (W/RB). The B0-B35 outputs are in
the high-impedance state when either CSB or W/RB is HIGH. The B0-B35
outputsareactivewhenbothCSBandW/RBareLOW. Dataisreadfromthe
FIFOtotheB0-B35outputsbyaLOW-to-HIGHtransitionofCLKBwhenCSB
isLOW,W/RBisLOW,ENBisHIGH,MBBisLOW,andEFisHIGH(seeTable
3). The relevant Read timing diagram for Port B can be found in Figure 4.
The setup and hold-time constraints to the port clocks for the port Chip
Selects(CSA,CSB)andWrite/Readselects(W/RA,W/RB)areonlyforenabling
write and read operations and are not related to HIGH-impedance control of
the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip
Select and Write/Read select can change states during the setup and hold-time
window of the cycle.
TABLE 1 – FLAG PROGRAMMING
TABLE 2 – PORT-A ENABLE FUNCTION TABLE
TABLE 3 – PORT-B ENABLE FUNCTION TABLE
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| IDT72V3611L15PF8 | 功能描述:IC FIFO SYNC 64X36 15NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3611L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 64X36 15NS 120TQFP |
| IDT72V3611L15PQF | 功能描述:IC FIFO SYNC 64X36 15NS 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3611L20PF | 功能描述:IC FIFO SYNC 64X36 20NS 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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