IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM <" />
參數(shù)資料
型號： IDT72V36110L7-5PFI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 14/48頁
文件大?。?/td> 0K
描述： IC FIFO 131KX36 7-5NS 128QFP
標準包裝： 36
系列： 72V
功能： 同步
存儲容量： 4.7M（131K x 36）
數(shù)據(jù)速率： 166MHz
訪問時間： 5ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應商設備封裝： 128-TQFP（14x20）
包裝： 托盤
其它名稱： 72V36110L7-5PFI
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (
FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR)toindicatewhetherornotthere
is valid data at the data outputs (Qn). It also uses Input Ready (
IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges,
REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (
REN) and RCLK.
AfterMasterReset,FWFT/SIactsasaserialinputforloading
PAEandPAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT
Standard and FWFT modes.
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedvia
ASYW,this
input behaves as WCLK.
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,the
FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating
HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe).
Data is Asynchronously written into the FIFO via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be tied LOW.
WRITE ENABLE (
WEN )
Whenthe
WENinput isLOW,datamaybeloadedintotheFIFORAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When
WENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode,
FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle,
IR will go
LOW allowing a write to occur. The
IR flag is updated by two WCLK cycles +
tSKEW after the valid RCLK cycle.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
If Asynchronous operation of the write port has been selected, then
WEN
must be held active, (tied LOW).
READ STROBE & READ CLOCK (RD/RCLK)
IfSynchronousoperationofthereadporthasbeenselectedvia
ASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,the
EF/OR,PAE
and
HF flagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
the
HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
If Asynchronous operation has been selected this input is RD (Read
Strobe) . Data is Asynchronously read from the FIFO via the output register
whenever there is a rising edge on RD. In this mode the
REN input must be
tied LOW. The
OEinputisusedtoprovideAsynchronouscontrolofthethree-
stateQnoutputs.
READ ENABLE (
REN )
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
When the
REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using
REN. Whenthelast
word has been read from the FIFO, the Empty Flag (
EF)willgoLOW,inhibiting
further read operations.
RENisignoredwhentheFIFOisempty.Onceawrite
is performed,
EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW
after the first write.
RENdoesnotneedtobeassertedLOW. Inordertoaccess
allotherwords,areadmustbeexecutedusing
REN. TheRCLKLOW-to-HIGH
transition after the last word has been read from the FIFO, Output Ready (
OR)
will go HIGH with a true read (RCLK with
REN = LOW), inhibiting further read
operations.
REN is ignored when the FIFO is empty.
If Asynchronous operation of the Read port has been selected, then
REN
must be held active, (tied LOW).
SERIAL ENABLE (
SEN )
The
SEN input isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset.
SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofWCLK.
When
SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN functions the same way in both IDT
Standard and FWFT modes.
OUTPUT ENABLE (
OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When
OEisHIGH,theoutputdatabus(Qn)goes
into a high impedance state.
LOAD (
LD )
This is a dual purpose pin. During Master Reset, the state of the
LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the
PAEand PAFflags,alongwiththemethodbywhichtheseoffsetregisters
can be programmed, parallel or serial (see Table 2). After Master Reset,
LD
enables write operations to and read operations from the offset registers. Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offset registers can be read only in parallel.
AfterMasterReset,the
LDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvalues
PAEandPAF.PullingLDLOWwillbeginaserialloading
or parallel load or read of these offset values.
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參數(shù)描述
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