參數(shù)資料
型號(hào): IDT72T6360L7-5BBI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 30/51頁(yè)
文件大?。?/td> 0K
描述: IC FLOW-CTRL 48BIT 7-5NS 324-BGA
標(biāo)準(zhǔn)包裝: 1
類型: 連續(xù)流量控制
安裝類型: 表面貼裝
封裝/外殼: 324-BGA
供應(yīng)商設(shè)備封裝: 324-PBGA(19x19)
包裝: 托盤
其它名稱: 72T6360L7-5BBI
36
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
Figure 12. Full Boundary - IDT Standard Mode
1
2
WCLK
WEN
D[35:0]
RCLK
6357 drw26
REN
Q[35:0]
FF
tDS
tDH
tENS
tENH
tSKEW1
tWFFs
tENS
tWFFs
tA
Previous Word in Register
Word 0
tA
Word 1
tA
Word 2
tA
Word 3
WD-1
WD
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle
(plus tWFFs). If tSKEW1 is not met, then
FF de-assertion may be delayed one extra WCLK cycle.
2. Settings:
OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
1
2
WCLK
WEN
D[35:0]
RCLK
6357 drw27
REN
Q[35:0]
IR
tDS
WD-1
tDH
tENS
tENH
tSKEW1
tWFFs
tENS
tWFFs
tA
Word 0
Word 1
tA
Word 2
tA
Word 3
tA
Word 4
WD
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH after one RCLK cycle
(plus tREFs). If tSKEW1 is not met, then
EF de-assertion may be delayed one extra RCLK cycle.
2. Settings:
RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH.
6ns
7-5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
tDS
DataSetupTime
2
2.5
ns
tDH
Data Hold Time
0.5
0.5
ns
tENS
Enable Setup Time
2
2.5
ns
tENH
Enable Hold Time
0.5
0.5
ns
tA
Data Access Time
1
4
1
5
ns
tWFFs
Write Clock to Synchronous
FF/IR
—4
—5
ns
tSKEW1
Skew time between RCLK and WCLK for
EF/OR and FF/IR in SDR
4
5
ns
Figure 13. Full Boundary - FWFT Mode
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