參數(shù)資料
型號(hào): IDT72T6360L7-5BBI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 28/51頁
文件大小: 0K
描述: IC FLOW-CTRL 48BIT 7-5NS 324-BGA
標(biāo)準(zhǔn)包裝: 1
類型: 連續(xù)流量控制
安裝類型: 表面貼裝
封裝/外殼: 324-BGA
供應(yīng)商設(shè)備封裝: 324-PBGA(19x19)
包裝: 托盤
其它名稱: 72T6360L7-5BBI
34
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
Figure 8. Write First Word Cycles - IDT Standard Mode
tENS
12
tA
Word 0
tA
tENS
tSKEW1
Word 0
tENH
WCLK
REN
WEN
D[35:0]
RCLK
6357 drw22
EF
Q[35:0]
tREFs
tENH
Word 1
Word 2
tENH
tREFs
tA
Word 1
Word 2
tENS
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH after one RCLK cycle
(plus tREFs). If tSKEW1 is not met, then
EF de-assertion may be delayed one extra RCLK cycle.
2. Settings:
OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
Figure 9. Write First Word Cycles - FWFT Mode
12
3
tA
Word 0
tA
tENS
tSKEW1
Word 0
tENH
WCLK
REN
WEN
D[35:0]
RCLK
6357 drw23
OR
Q[35:0]
tREFs
tENS
tENH
Word 1
Word 2
tENH
tREFs
tA
Word 1
Word 2
tENS
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH after one RCLK cycle
(plus tREFs). If tSKEW1 is not met, then
EF de-assertion may be delayed one extra RCLK cycle.
2. Settings:
OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1000, FWFT = HIGH, ASYR = HIGH, and ASYW = HIGH.
6ns
7-5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
tSENS
Serial Enable Setup
5
5
ns
tSENH
Serial Enable Hold
5
5
ns
tA
Data Access Time
1
4
1
5
ns
tSKEW1
Skew time between RCLK and WCLK for
EF/OR
4—
5
ns
and
FF/IR in SDR
tREFs
Read Clock to Synchronous
EF/OR
—4
5
ns
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