參數(shù)資料
型號(hào)： IDT72T6360L7-5BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁(yè)數(shù)： 41/51頁(yè)
文件大小： 508K
代理商： IDT72T6360L7-5BBI
46
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 10, 2005
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test, then it will be executed when the controller enters this state. The test logic
in the IC is idle otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
other wise.
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Figure 33. TAP Controller State Diagram
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising
edge of TCK. The instruction available on the TDI pin is also shifted in to the
instruction register. TDO changes on the falling edge of TCK.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DRThis is a controller state where a decision to enter either the Shift-
IR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register
scanchainislatchedintotheregisteroftheInstructionRegisteroneveryfalling
edgeofTCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
Test-Logic
Reset
Run-Test/
Idle
1
0
Select-
DR-Scan
Select-
IR-Scan
1
Capture-IR
0
Capture-DR
0
Exit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
0
1
6357 drw47
0
Shift-DR
0
Shift-IR
0
Pause-IR
0
1
Input is
TMS
0
1
NOTES:
1. Five consecutive 1's at TMS will reset the TAP.
2. TAP controller resets automatically upon power-up.
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