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參數(shù)資料
| 型號： | IDT72T6360L6BBGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 1/51頁 |
| 文件大小： | 508K |
| 代理商： | IDT72T6360L6BBGI |
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1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6357/4
OCTOBER 2005
2.5V SEQUENTIAL FLOW-CONTROL DEVICE
36 BIT WIDE CONFIGURATION
For use with 128Mb to 256Mb DDR SDRAM
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72T6360
FEATURES
Product to be used with single or multiple external DDR SDRAM
to provide significant storage capability of up to 1Gb density
166MHz operation (6ns read/write cycle time)
User selectable input and output port bus-sizing
- x36in to x36out
- x36in to x18out
- x36in to x9out
- x18in to x36out
- x18in to x18out
- x18in to x9out
- x9in to x36out
- x9in to x18out
- x9in to x9out
For other bus configurations see IDT72T6480 (x12, x24, or x48)
2.5V-LVTTL or 3.3V-LVTTL configured ports
Independent and simultaneous read and write access
User selectable synchronous/asynchronous read and write
port timing
IDT Standard mode or FWFT mode of operation
Empty and full flags for monitoring memory status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of four preselected offsets or serially
programmed to a specific value
Selectable synchronous/asynchronous timing modes for
Almost-Empty and Almost-Full flags
Master Reset clears all data and settings
Partial Reset clears data, but retains programmable settings
Depth expandable with multiple devices for densities greater
than 1Gb
Width expandable with multiple devices for bus widths greater
than 36 bits
JTAG functionality (Boundary Scan)
Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm
HIGH performance 0.18
m CMOS technology
Industrial temperature range (-40
°°°°°C to +85°°°°°C) is available
Supports industry standard DDR specifications, including
Samsung, Micron, and Infineon memories
FUNCTIONAL BLOCK DIAGRAM
36-
bi
ts
36-
bi
ts
36-
bi
ts
6357 drw01
x36, x18, or x9
High Density DDR SDRAM
x16, x32, x36, or x64
128Mb to 256Mb
64
DDR SDRAM
Control Logic
x36, x18, or x9
IDT72T6360
Sequential Flow Control Device
Data
Addr
CK
WE CAS RAS
Flag
Logic
JTAG
Control
(Boundary Scan)
FWFT
FSEL[1:0]
FF/IR
PAF
PAE
Write
Control
Logic
R
ead
Co
n
tro
lL
o
gic
Reset
Logic
MRS
PRS
I/O
Bus
Configuration
IOSEL
BM[3:0]
WEN
WCLK/WR
REN
RCLK/RD
RCS
Input
Register
EF/OR
Output
Register
WCS
ASYW
MCLK
ASYR
DQS
TCK/SCLK
TMS
TDO/SO
TDI/SI
13
8
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| IDT72T6360L7-5BB | 功能描述:IC FLOW-CTRL 48BIT 7-5NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6360L7-5BBI | 功能描述:IC FLOW-CTRL 48BIT 7-5NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6480L10BB | 功能描述:IC FLOW-CTRL 48BIT 10NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6480L10BBI | 功能描述:IC FLOW-CTRL 48BIT 10NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6480L7-5BB | 功能描述:IC FLOW-CTRL 48BIT 7-5NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
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