參數(shù)資料
型號： IDT72T6360L7-5BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù)： 40/51頁
文件大?。?/td> 508K
代理商： IDT72T6360L7-5BBI
45
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 10, 2005
JTAG TIMING SPECIFICATIONS
(IEEE 1149.1 COMPLIANT)
The JTAG test port in this device is fully compliant with the IEEE Standard
TestAccessPort(IEEE1149.1)specifications.Fouradditionalpins(TDI,TDO,
TMS and TCK) are provided to support the JTAG boundary scan interface.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The Standard JTAG interface consists of seven basic elements:
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Bypass Register (BYR)
ID Code Register
The following sections provide a brief description of each element. For a
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
Figure 32. JTAG Architecture
TEST ACCESS PORT (TAP)
The TAP interface is a general-purpose port that provides access to the
internal JTAG state machine. It consists of three input ports (TCLK, TMS, TDI)
and one output port (TDO).
THE TAP CONTROLLER
The TAP controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and updating of data passed through the TDI
serial input.
In Pad
Incell
Core
Logic
Outcell
Out Pad
All outputs
All inputs
Eg: Dins, Clks
(BSDL file
describes the
chain order)
ID
Bypass
Instruction
Register
TAP
TMS
TDI
TCK
Instruction
Select
Enable
TDO
6357 drw46
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