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| 型號： | IDT72T36135ML6BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/48頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO 1MX18 6NS 240BGA |
| 標準包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 18M（1M x 18） |
| 數(shù)據(jù)速率： | 166MHz |
| 訪問時間： | 3.8ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36135ML6BB |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
21
FEBRUARY 04, 2009
READ CHIP SELECT (
RCS )
The Read Chip Select input provides synchronous control of the Read
output port. When
QnoutputstogototheLow-Impedancestate. When
RCSgoesHIGH,thenext
RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master
orPartialResetthe
RCSinputhasnoeffectontheQnoutputbus,OEistheonly
inputthatprovidesHigh-ImpedancecontroloftheQnoutputs.If
OEisLOWthe
Qn data outputs will be Low-Impedance regardless of
RCSuntilthefirstrising
edge of RCLK after a Reset is complete. Then if
RCSisHIGHthedataoutputs
will go to High-Impedance.
The
RCSinputdoesnoteffecttheoperationoftheflags. Forexample,when
the first word is written to an empty FIFO, the
EF[1:2] will still go from LOW to
HIGHbasedonarisingedgeofRCLK
,regardlessofthestateoftheRCSinput.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of
RCS. For this reason the user must take care when
adatawordiswrittentoanemptyFIFOinFWFTmode.If
RCSisdisabledwhen
anemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutputregister,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take
RCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z.
RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW.
A rising edge of RCLK with
RCS and REN active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty
FIFO when
RCSisHIGH.RefertoFigure16,RCS andREN ReadOperation
(FWFT Mode). The
RCS pin must also be active (LOW) in order to perform
aRetransmit. SeeFigure12forReadCycleandReadChipSelectTiming(IDT
Standard Mode). See Figure 15 for Read Cycle and Read Chip Select Timing
(First Word Fall Through Mode).
If Asynchronous operation of the Read port has been selected, then
RCS
must be held active, (tied LOW).
OE provides three-state control of Qn.
WRITE PORT HSTL SELECT (WHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththewriteport
can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master
Reset,thenHSTLoperationofthewriteportwillbeselected.IfWHSTLisLOW
at Master Reset, then LVTTL will be selected.
The inputs and outputs associated with the write port are listed in Table 4,
I/O Configuration.
READ PORT HSTL SELECT (RHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththereadport
can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master
Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW
at Master Reset, then LVTTL will be selected for the read port.
The inputs and outputs associated with the read port are listed in Table 4,
I/O Configuration.
SYSTEM HSTL SELECT (SHSTL)
Allinputsnotassociatedwiththewriteandreadportcanbesetuptobeeither
HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation
of all the inputs not associated with the write and read port will be selected. If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associated with SHSTL are listed in Table 4, I/O Configuration.
LOAD (
LD)
This is a dual purpose pin. During Master Reset, the state of the
LDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
the
PAE[1:2]andPAF[1:2]flags,alongwiththemethodbywhichtheseoffset
registers can be programmed, parallel or serial (see Table 1). After Master
Reset,
LD enables write operations to and read operations from the offset
registers.Onlytheoffsetloadingmethodcurrentlyselectedcanbeusedtowrite
to the registers. Offset registers can be read only in parallel.
AfterMasterReset,the
LDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvalues
PAE[1:2]andPAF[1:2].PullingLDLOWwillbeginaserial
loadingorparallelloadorreadoftheseoffsetvalues. THISPINMUSTBEHIGH
AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO
MEMORY.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mable flag timing mode. A HIGH on PFM will select Synchronous Program-
mableflagtimingmode.Ifasynchronous
PAF/PAE[1:2]configurationisselected
(PFM,LOWduring
MRS),thePAE[1:2]isassertedLOWontheLOW-to-HIGH
transition of RCLK.
PAE[1:2]isresettoHIGHontheLOW-to-HIGHtransition
of WCLK. Similarly, the
PAF[1:2] is asserted LOW on the LOW-to-HIGH
transitionofWCLKand
PAF[1:2]isresettoHIGHontheLOW-to-HIGHtransition
of RCLK.
Ifsynchronous
PAE/PAF[1:2]configurationisselected(PFM,HIGHduring
MRS) , the
PAE[1:2]isassertedandupdatedontherisingedgeofRCLKonly
and not WCLK. Similarly,
PAF[1:2]isassertedandupdatedontherisingedge
of WCLK only and not RCLK. The mode desired is configured during master
reset by the state of the Programmable Flag Mode (PFM) pin.
OUTPUTS:
FULL FLAG (
FF/IR[1:2] )
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FF[1:2])
functionisselected.WhentheFIFOisfull,
FF[1:2]willgoLOW,inhibitingfurther
write operations. When
FF[1:2] is HIGH, the FIFO is not full. If no reads are
performedafterareset(either
MRSorPRS),FF[1:2]willgoLOWafterDwrites
to the FIFO (D = 524,288 for the IDT72T36135M). See Figure 10, Write Cycle
and Full Flag Timing (IDT Standard Mode), for the relevant timing information.
Please see Flagging section for external gating instructions of these flags.
In FWFT mode, the Input Ready (
IR[1:2])functionisselected.IR[1:2]goes
LOW when memory space is available for writing in data. When there is no
longeranyfreespaceleft,
IR[1:2]goesHIGH,inhibitingfurtherwriteoperations.
Ifnoreadsareperformedafterareset(either
MRSorPRS),IR[1:2]willgoHIGH
after D writes to the FIFO (D = 524,288 for the IDT72T36135M). See Figure
13, Write Timing (FWFT Mode), for the relevant timing information.
The
IR[1:2]statusnotonlymeasuresthecontentsoftheFIFOmemory,but
alsocountsthepresenceofawordintheoutputregister. Thus,inFWFTmode,
the total number of writes necessary to deassert
IR[1:2] is one greater than
needed to assert
FF[1:2] in IDT Standard mode.
FF/IR[1:2] is synchronous and updated on the rising edge of WCLK. FF/
IR[1:2]aredoubleregister-bufferedoutputs.
Note, when the device is in Retransmit mode, this flag is a comparison of
the write pointer to the ‘marked’ location. This differs from normal mode where
this flag is a comparison of the write pointer to the read pointer.
EMPTY FLAG (
EF/OR[1:2] )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(
EF[1:2])functionisselected. WhentheFIFOisempty, EF[1:2] willgoLOW,
inhibitingfurtherreadoperations. When
EF[1:2]isHIGH,theFIFOisnotempty.
See Figure 11, Read Cycle, Empty Flag and First Word Latency Timing (IDT
Standard Mode), for the relevant timing information. Please see Flagging
section for external gating instructions of these flags.
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