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參數(shù)資料
| 型號： | IDT72T36135ML6BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 1MX18 6NS 240BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 18M（1M x 18） |
| 數(shù)據(jù)速率： | 166MHz |
| 訪問時間： | 3.8ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36135ML6BB |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
19
FEBRUARY 04, 2009
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Data inputs for 36-bit wide data (D0 - D35).
CONTROLS:
MASTER RESET (
MRS )
AMasterResetisaccomplishedwheneverthe
MRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
of the RAM array.
PAE[1:2] will go LOW, PAF[1:2] will go HIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with
EF[1:2] andFF[1:2] areselected.EF[1:2] willgoLOWandFF[1:2]
will go HIGH. If FWFT/SI is HIGH, then the First Word Fall Through mode
(FWFT), along with
IR[1:2] and OR[1:2], are selected. OR[1:2] will go HIGH
and
IR[1:2] will go LOW.
AllcontrolsettingssuchasRMandPFMaredefinedduringtheMasterReset
cycle.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Reset is required after power up, before a write operation can take place.
MRS
is asynchronous.
See Figure 8, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (
PRS)
APartialResetisaccomplishedwheneverthe
PRS inputistakentoaLOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array,
PAE[1:2] goes LOW, PAF[1:2]
goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then
FF[1:2]willgoHIGHandEF[1:2]willgoLOW. IftheFirst
Word Fall Through mode is active, then
OR[1:2]willgoHIGH,andIR[1:2]will
go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes.
PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
See Figure 9, Partial Reset Timing, for the relevant timing diagram.
ASYNCHRONOUS WRITE (
ASYW)
The write port can be configured for either Synchronous or Asynchronous
mode of operation. If during Master Reset the
ASYW input is LOW, then
Asynchronous operation of the write port will be selected. During Asynchro-
nous operation of the write port the WCLK input becomes WR input, this is the
Asynchronous write strobe input. A rising edge on WR will write data present
on the Dn inputs into the FIFO. (
WEN mustbetiedLOWwhenusingthewrite
port in Asynchronous mode).
When the write port is configured for Asynchronous operation the full flag
(
FF[1:2]) operates in an asynchronous manner, that is, the full flag will be
updatedbasedinbothawriteoperationandreadoperation.Note,ifAsynchro-
nous mode is selected, FWFT is not permissable. Refer to Figures 30, 31, 34
and 35 for relevant timing and operational waveforms.
ASYNCHRONOUS READ (
ASYR)
The read port can be configured for either Synchronous or Asynchronous
mode of operation. If during a Master Reset the
ASYR input is LOW, then
Asynchronous operation of the read port will be selected. During Asynchro-
nous operation of the read port the RCLK input becomes RD input, this is the
Asynchronous read strobe input. A rising edge on RD will read data from the
FIFO via the output register and Qn port. (
REN must be tied LOW during
Asynchronous operation of the read port).
The
OE input provides three-state control of the Qn output bus, in an
asynchronous manner. (
RCS,providesthree-statecontrolofthereadportin
Synchronous mode).
When the read port is configured for Asynchronous operation the device
must be operating on IDT standard mode, FWFT mode is not permissible if the
read port is Asynchronous. The Empty Flag (
EF[1:2]) operates in an
Asynchronous manner, that is, the empty flag will be updated based on both
a read operation and a write operation. Refer to figures 32, 33, 34 and 35 for
relevant timing and operational waveforms.
RETRANSMIT (
RT)
The Retransmit (
RT) input is used in conjunction with the MARK input,
together they provide a means by which data previously read out of the FIFO
can be reread any number of times. If retransmit operation has been selected
(i.e.theMARKinputisHIGH),arisingedgeonRCLKwhile
RTisLOWwillreset
thereadpointerbacktothememorylocationsetbytheuserviatheMARKinput.
If IDT standard mode has been selected the
EF[1:2] flagwillgoLOWand
remain LOW for the time that
RT is held LOW. RT can be held LOW for any
number of RCLK cycles, the read pointer being reset to the marked location.
The next rising edge of RCLK after
RT hasreturnedHIGH,willcauseEF[1:2]
to go HIGH, allowing read operations to be performed on the FIFO. The next
read operation will access data from the ‘marked’ memory location.
Subsequent retransmit operations may be performed, each time the read
pointerreturningtothe‘marked’location.SeeFigure17,RetransmitfromMark
(IDT Standard mode) for the relevant timing diagram.
If FWFT mode has been selected the
OR[1:2]flagwillgoHIGHandremain
HIGH for the time that
RT is held LOW. RT can be held LOW for any number
of RCLK cycles, the read pointer being reset to the ‘marked’ location. The next
RCLK rising edge after
RT hasreturnedHIGH,willcauseOR[1:2] to go LOW
and due to FWFT operation, the contents of the marked memory location will
be loaded onto the output register, a read operation being required for all
subsequentdatareads.
Subsequent retransmit operations may be performed each time the read
pointerreturningtothe‘marked’location.SeeFigure18,RetransmitfromMark
(FWFT mode) for the relevant timing diagram.
MARK
The MARK input is used to select Retransmit mode of operation. An RCLK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmitmode.FortheIDT72T36135Maminimumof128words(x36).Also,
once the MARK is set, the write pointer will not increment past the “marked”
locationuntiltheMARKisdeasserted.Thisprevents“overwriting”ofretransmit
data.
The MARK input must remain HIGH during the whole period of retransmit
mode, a falling edge of RCLK while MARK is LOW will take the device out of
retransmitmodeandintonormalmode.AnynumberofMARKlocationscanbe
set during FIFO operation, only the last marked location taking effect. Once a
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